Patents by Inventor Kazumasa Tanida

Kazumasa Tanida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7432196
    Abstract: The invention provides a semiconductor chip manufacturing method, including a step of forming a front-surface-side concave portion in a semiconductor substrate having a front surface and a rear surface, a functional device being formed on the front surface, the front-surface-side concave portion being formed in the front surface and having a predetermined depth smaller than a thickness of the semiconductor substrate; a dummy plug forming step of supplying nonmetallic material into the front-surface-side concave portion and embedding a dummy plug made of the nonmetallic material; a thinning step of removing a part of the rear surface of the substrate and thinning the semiconductor substrate so that the thickness of the semiconductor substrate becomes smaller than the depth of the front-surface-side concave portion and so that the front-surface-side concave portion is formed into a through-hole; a dummy plug removing step of removing the dummy plug; and a step of supplying metallic material into the through-hol
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: October 7, 2008
    Assignees: Rohm Co., Ltd., Renesas Technology Corp., Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Tanida, Yoshihiko Nemoto, Kenji Takahashi
  • Patent number: 7416963
    Abstract: This invention offers a manufacturing method to reduce a manufacturing cost of a semiconductor device having a through-hole electrode by simplifying a manufacturing process and to enhance yield of the semiconductor device. A first insulation film is formed on a top surface of a semiconductor substrate. A part of the first insulation film is etched to form an opening in which a part of the semiconductor substrate is exposed. Then a pad electrode is formed in the opening and on the first insulation film. A second insulation film is formed on a back surface of the semiconductor substrate. Then a via hole having an aperture larger than the opening is formed. And a third insulation film is formed in the via hole and on the second insulation film. The third insulation film on a bottom of the via hole is etched to expose the pad electrode. After that, a through-hole electrode and a wiring layer are formed in the via hole.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: August 26, 2008
    Inventors: Mitsuo Umemoto, Yoshio Okayama, Kazumasa Tanida, Hiroshi Terao, Yoshihiko Nemoto
  • Patent number: 7405485
    Abstract: A semiconductor device provided with a first semiconductor chip having a first functional surface formed with a first functional element and a first rear surface, a second semiconductor chip having a second functional surface which is formed with a second functional element, the second functional surface having a region opposed to the first functional surface of the first semiconductor chip and a non-opposed region defined outside the opposed region, a connection member electrically connecting the first functional element and the second functional element, an insulation film continuously covering the non-opposed region of the second semiconductor chip and the first rear surface of the first semiconductor chip, a rewiring layer provided on a surface of the insulation film, a protective resin layer covering the rewiring layer, and an external connection terminal projecting from the rewiring layer through the protective resin layer.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: July 29, 2008
    Assignee: Rohm Co., Ltd.
    Inventors: Kazumasa Tanida, Tadahiro Morifuji, Osamu Miyata
  • Publication number: 20080036043
    Abstract: A manufacture method for semiconductor device (1, 21) including: a sealing-resin-layer forming step of forming a sealing resin layer (7) on a conductive member (13) formed at lest on one surface of a base substrate (11) formed with a plurality of wiring boards (2) therein, the conductive member spanning a boundary between a respective pair of adjoining wiring boards; and a step of moving the base substrate and a cutting tool (B) relative to each other in a manner to allow the cutting tool to pass through the base substrate from the other surface (2b) opposite from the one surface thereof toward the one surface thereof, thereby cutting the base substrate along the boundary between the respective pair of adjoining wiring boards.
    Type: Application
    Filed: October 17, 2005
    Publication date: February 14, 2008
    Applicant: ROHM CO., LTD.
    Inventors: Kazumasa Tanida, Osamu Miyata
  • Publication number: 20070284735
    Abstract: A semiconductor device (1, 1A, 21, 31, 41, 51) provided with a first semiconductor chip (3) having a first functional surface (3F) formed with a first functional element (3a), a protective resin layer (12) provided on the first functional surface, and an external connection terminal (10, 19, 52) provided on a peripheral portion of the first functional surface for external electrical connection, the external connection terminal having a bottom surface (10B, 19BB) exposed from a bottom surface (12B) of the protective resin layer facing away from the first functional surface and a side surface (10S, 19BS) exposed from a side surface (12S) of the protective resin layer.
    Type: Application
    Filed: October 6, 2005
    Publication date: December 13, 2007
    Inventors: Kazumasa Tanida, Shigo Higuchi, Takuya Kadoguchi
  • Patent number: 7306972
    Abstract: The invention realizes excellent electrical and mechanical connection between electrodes in a packaging structure where a plurality of semiconductor chips having electrodes are connected with each other through the low-melting metallic members. Bump electrodes are formed on a front surface of a first semiconductor chip. Penetrating holes are formed in a second semiconductor chip, and a penetrating electrode having a gap in a center is formed in each of the penetrating holes. Low-melting metallic members are interposed between connecting surfaces of the bump electrodes and the penetrating electrodes, and a part of each of the low-melting metallic members flows in each of the gaps of the penetrating electrodes when dissolved. This prevents short-circuiting between the bump electrodes which is caused by oversupplying the low-melting metallic members between the adjacent bump electrodes.
    Type: Grant
    Filed: February 14, 2006
    Date of Patent: December 11, 2007
    Assignees: Sanyo Electric Co., Ltd., Rohm Co., Ltd.
    Inventors: Mitsuo Umemoto, Kazumasa Tanida
  • Patent number: 7282444
    Abstract: The invention provides a semiconductor chip manufacturing method including the steps of: forming a concave portion extended in the thickness direction of a semiconductor substrate which has a front surface and a rear surface and has a function device formed on the front surface, from the front surface; forming an oxidation preventive film made of an inert first metal material by supplying the first metal material onto the inner wall surface of the concave portion; supplying a second metal material containing a metal which is oxidized more easily than the first metal material to the inside of the concave portion after the step of forming the oxidation preventive film; electrically connecting the second metal material supplied to the inside of the concave portion and the function device; and thinning the semiconductor substrate so that the thickness thereof becomes thinner than the depth of the concave portion by removing the semiconductor substrate from the rear surface while leaving the oxidation preventive f
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: October 16, 2007
    Assignees: Rohm Co., Ltd., Renesas Technology Corp., Sanyo Electric Co., Ltd., Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Tanida, Mitsuo Umemoto, Yoshihiko Nemoto, Kenji Takahashi
  • Publication number: 20070230153
    Abstract: A semiconductor device is provided with: a solid device having a connection surface formed with a connection electrode projected therefrom; a semiconductor chip which has a functional surface formed with a metal bump projected therefrom and which is bonded to the connection surface of the solid device as directing its functional surface to the connection surface and maintaining a predetermined distance between the functional surface and the connection surface; and a connecting member containing a low melting point metal having a lower solidus temperature than that of the connection electrode and the bump, and interconnecting the connection electrode and the bump. A sum of a height of the connection electrode and a height of the bump is not less than a half of the predetermined distance.
    Type: Application
    Filed: September 1, 2005
    Publication date: October 4, 2007
    Inventors: Kazumasa Tanida, Osamu Miyata
  • Publication number: 20070200249
    Abstract: The invention provides a wiring board (2,15) to which a semiconductor chip (3) is to be bonded while directing a surface of the semiconductor chip toward the wiring board. The wiring board includes a connection electrode (14) that is formed on a bonding surface (2a, 15a) to which the semiconductor chip is to be bonded and that is used to make a connection with the semiconductor chip, an insulating film (6) that is formed on the bonding surface and that has an opening (6a) to expose the connection electrode, and a low-melting-point metallic part (16) that is provided on the connection electrode in the opening and that is made of a low-melting-point metallic material whose solidus temperature is lower than that of the connection electrode.
    Type: Application
    Filed: August 4, 2005
    Publication date: August 30, 2007
    Applicant: ROHM CO., LTD.
    Inventors: Kazumasa Tanida, Osamu Miyata
  • Patent number: 7259454
    Abstract: The invention provides a semiconductor chip manufacturing method, including a step of forming a front-surface-side concave portion in a semiconductor substrate having a front surface and a rear surface, a functional device being formed on the front surface, the front-surface-side concave portion being formed in the front surface and having a predetermined depth smaller than a thickness of the semiconductor substrate; a dummy plug forming step of supplying nonmetallic material into the front-surface-side concave portion and embedding a dummy plug made of the nonmetallic material; a thinning step of removing a part of the rear surface of the substrate and thinning the semiconductor substrate so that the thickness of the semiconductor substrate becomes smaller than the depth of the front-surface-side concave portion and so that the front-surface-side concave portion is formed into a through-hole; a dummy plug removing step of removing the dummy plug; and a step of supplying metallic material into the through-hol
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: August 21, 2007
    Assignees: Rohm Co., Ltd., Renesas Technology Corp., Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Tanida, Yoshihiko Nemoto, Kenji Takahashi
  • Patent number: 7253527
    Abstract: A semiconductor chip production method including the steps of: forming a front side recess in a semiconductor substrate; depositing a metal material in the front side recess to form a front side electrode electrically connected to a functional device formed on the front surface; removing a rear surface portion of the semiconductor substrate to reduce the thickness of the semiconductor substrate to a thickness greater than the depth of the front side recess; forming a rear side recess communicating with the front side recess in the rear surface of the semiconductor substrate after the thickness reducing step; and depositing a metal material in the rear side recess to form a rear side electrode electrically connected to the front side electrode for formation of a through-electrode.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: August 7, 2007
    Assignees: Rohm Co., Ltd., Renesas Technology Corporation
    Inventors: Kazumasa Tanida, Yoshihiko Nemoto, Naotaka Tanaka
  • Publication number: 20070155155
    Abstract: A manufacturing method for a semiconductor device, including the steps of: forming a passivation film that covers a surface of a semiconductor substrate on which electrodes have been formed, in which an opening is formed so as to expose a predetermined electrode from among the electrodes; forming a diffusion prevention plug of a first metal in the vicinity of the opening in the passivation film; supplying a second metal material to the surface of the semiconductor substrate on which the diffusion prevention plug has been formed, so as to form a seed layer of the second metal; forming a resist film that covers the seed layer and in which an opening is formed so as to expose a predetermined region of the seed layer on the diffusion prevention plug; supplying a third metal material into the opening in the resist film so as to form a protrusion electrode of the third metal; removing the resist film after the step of forming a protrusion electrode; and removing the seed layer after the step of forming a protrusion
    Type: Application
    Filed: March 13, 2007
    Publication date: July 5, 2007
    Inventors: Kazumasa Tanida, Yoshihiko Nemoto, Mitsuo Umemoto
  • Patent number: 7235428
    Abstract: A semiconductor device production method including: the step of forming a stopper mask layer of a first metal on a semiconductor substrate, the stopper mask layer having an opening at a predetermined position thereof; the metal supplying step of supplying a second metal into the opening of the stopper mask layer to form a projection electrode of the second metal; and removing the stopper mask layer after the metal supplying step.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: June 26, 2007
    Assignees: Rohm Co., Ltd., Mitsubishi Denki Kabushiki Kaisha, Sanyo Electric Co., Ltd.
    Inventors: Kazumasa Tanida, Yoshihiko Nemoto, Mitsuo Umemoto
  • Patent number: 7227262
    Abstract: A manufacturing method for a semiconductor device, including the steps of: forming a passivation film that covers a surface of a semiconductor substrate on which electrodes have been formed, in which an opening is formed so as to expose a predetermined electrode from among the electrodes; forming a diffusion prevention plug of a first metal in the vicinity of the opening in the passivation film; supplying a second metal material to the surface of the semiconductor substrate on which the diffusion prevention plug has been formed, so as to form a seed layer of the second metal; forming a resist film that covers the seed layer and in which an opening is formed so as to expose a predetermined region of the seed layer on the diffusion prevention plug; supplying a third metal material into the opening in the resist film so as to form a protrusion electrode of the third metal; removing the resist film after the step of forming a protrusion electrode; and removing the seed layer after the step of forming a protrusion
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: June 5, 2007
    Assignees: Rohm Co., Ltd., Renesas Technology Corp., Sanyo Electric Co., Ltd.
    Inventors: Kazumasa Tanida, Yoshihiko Nemoto, Mitsuo Umemoto
  • Publication number: 20070080457
    Abstract: A manufacturing method for a semiconductor device includes: the step of preparing a semiconductor chip which is provided with a functional element formed on a front surface side of a semiconductor substrate, a feedthrough electrode which is placed within a through hole that penetrates the semiconductor substrate, a front surface side connection member which protrudes from the front surface, and a rear surface side connection member which has a joining surface within a recess that is formed in a rear surface; the step of preparing a solid state device where a solid state device side connection member for connection to the front surface side connection member is formed on one surface; and the joining step of making the front surface of the semiconductor chip face the first surface of the solid state device by holding the rear surface of the semiconductor chip, and of joining the front surface side connection member to the solid state device side connection member.
    Type: Application
    Filed: December 7, 2006
    Publication date: April 12, 2007
    Inventors: Kazumasa Tanida, Mitsuo Umemoto, Yukiharu Akiyama
  • Patent number: 7169639
    Abstract: The invention relates to a semiconductor device manufacturing method which can provide high reliability in electric connection between an electrode of a semiconductor chip and a substrate. Sealing resin is coated in a region of a substrate where a first electrode is not formed. A semiconductor chip formed with a second electrode on its end portion is prepared and disposed so as to face to a front surface of the substrate. The end portion of the semiconductor chip is pressed from its back surface by shifting a first movable plate downward to press the second electrode into contact with the first electrode. After then, a center portion of the semiconductor chip is pressed from its back surface by shifting a second movable plate downward to fill a space between the substrate and the semiconductor chip with the sealing resin.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: January 30, 2007
    Assignees: Sanyo Electric Co., Ltd., Rohm Co., Ltd.
    Inventors: Mitsuo Umemoto, Kazumasa Tanida
  • Publication number: 20070018320
    Abstract: A semiconductor chip production method including the steps of: forming a front side recess in a semiconductor substrate; depositing a metal material in the front side recess to form a front side electrode electrically connected to a functional device formed on the front surface; removing a rear surface portion of the semiconductor substrate to reduce the thickness of the semiconductor substrate to a thickness greater than the depth of the front side recess; forming a rear side recess communicating with the front side recess in the rear surface of the semiconductor substrate after the thickness reducing step; and depositing a metal material in the rear side recess to form a rear side electrode electrically connected to the front side electrode for formation of a through-electrode.
    Type: Application
    Filed: September 12, 2006
    Publication date: January 25, 2007
    Applicants: ROHM CO., LTD., RENESAS TECHNOLOGY CORPORATION
    Inventors: Kazumasa Tanida, Yoshihiko Nemoto, Naotaka Tanaka
  • Publication number: 20060267206
    Abstract: The invention provides a semiconductor chip manufacturing method, including a step of forming a front-surface-side concave portion in a semiconductor substrate having a front surface and a rear surface, a functional device being formed on the front surface, the front-surface-side concave portion being formed in the front surface and having a predetermined depth smaller than a thickness of the semiconductor substrate; a dummy plug forming step of supplying nonmetallic material into the front-surface-side concave portion and embedding a dummy plug made of the nonmetallic material; a thinning step of removing a part of the rear surface of the substrate and thinning the semiconductor substrate so that the thickness of the semiconductor substrate becomes smaller than the depth of the front-surface-side concave portion and so that the front-surface-side concave portion is formed into a through-hole; a dummy plug removing step of removing the dummy plug; and a step of supplying metallic material into the through-hol
    Type: Application
    Filed: August 3, 2006
    Publication date: November 30, 2006
    Inventors: Kazumasa Tanida, Yoshihiko Nemoio, Kenji Takahashi
  • Publication number: 20060267186
    Abstract: A semiconductor device provided with a first semiconductor chip having a first functional surface formed with a first functional element and a first rear surface, a second semiconductor chip having a second functional surface which is formed with a second functional element, the second functional surface having a region opposed to the first functional surface of the first semiconductor chip and a non-opposed region defined outside the opposed region, a connection member electrically connecting the first functional element and the second functional element, an insulation film continuously covering the non-opposed region of the second semiconductor chip and the first rear surface of the first semiconductor chip, a rewiring layer provided on a surface of the insulation film, a protective resin layer covering the rewiring layer, and an external connection terminal projecting from the rewiring layer through the protective resin layer.
    Type: Application
    Filed: June 9, 2005
    Publication date: November 30, 2006
    Inventors: Kazumasa Tanida, Tadahiro Morifuji, Osamu Miyata
  • Patent number: 7122457
    Abstract: A semiconductor chip production method including the steps of: forming a front side recess in a semiconductor substrate; depositing a metal material in the front side recess to form a front side electrode electrically connected to a functional device formed on the front surface; removing a rear surface portion of the semiconductor substrate to reduce the thickness of the semiconductor substrate to a thickness greater than the depth of the front side recess; forming a rear side recess communicating with the front side recess in the rear surface of the semiconductor substrate after the thickness reducing step; and depositing a metal material in the rear side recess to form a rear side electrode electrically connected to the front side electrode for formation of a through-electrode.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: October 17, 2006
    Assignee: Renesas Technology Corporation
    Inventors: Kazumasa Tanida, Yoshihiko Nemoto, Naotaka Tanaka