Patents by Inventor Kazumasa Tanida
Kazumasa Tanida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160126136Abstract: A semiconductor device according to an embodiment includes a low-adhesion film, a pair of substrates, and a metal electrode. The low-adhesion film has lower adhesion to metal than a semiconductor oxide film. The pair of substrates is provided with the low-adhesion film interposed therebetween. The metal electrode passes through the low-adhesion film and connects the pair of substrates, and includes, between the pair of substrates, a part thinner than parts embedded in the pair of substrates. A portion of the metal electrode embedded in one substrate is provided with a gap interposed between the portion and the low-adhesion film on the other substrate.Type: ApplicationFiled: October 30, 2015Publication date: May 5, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Hiroaki ASHIDATE, Kazumasa TANIDA
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Publication number: 20160126087Abstract: A method of manufacturing a semiconductor device according to an embodiment includes forming an opening in a surface of an insulating layer which is provided in a surface of a first substrate and a surface of a second substrate. The method includes filling the opening with metal. The method includes activating the surface of the insulating layer. The method includes cleaning the surface of the metal filled in the opening of the first substrate using carbonated water. The method includes connecting the filled metal of the first substrate and the filled metal of the second substrate by bonding the insulating layer of the first substrate and the insulating layer of the second substrate.Type: ApplicationFiled: September 9, 2015Publication date: May 5, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Kazumasa TANIDA, Hiroaki Ashidate
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Publication number: 20160035766Abstract: A semiconductor device such as, for example an imaging sensor, includes a semiconductor layer in which, for example, a photodiode may be formed. An insulation film is disposed on a surface of the semiconductor layer. The insulation film includes one or more wirings or wiring layers formed therein. A semiconductor support substrate is disposed on the insulation film. The semiconductor support substrate includes a first layer (or region) and a second layer (or region) that is between the insulation film and the first layer. The first layer has a bulk micro defect density that is higher than a bulk micro defect density of the second layer.Type: ApplicationFiled: February 17, 2015Publication date: February 4, 2016Inventors: Satoshi HONGO, Tsuyoshi MATSUMURA, Hiroaki ASHIDATE, Kazumasa TANIDA
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Publication number: 20160013099Abstract: According to embodiments, a semiconductor device is provided. The semiconductor device includes an insulation layer, an electrode, and a groove. The insulation layer is provided on a surface of a substrate. The electrode is buried in the insulation layer, and a first end surface of the electrode is exposed from the insulation layer. The groove is formed around the electrode on the surface of the substrate. The groove has an outside surface of the electrode as one side surface, and the groove is opened on the surface side of the insulation layer. The first end surface of the electrode buried in the insulation layer protrudes from the surface of the insulation layer.Type: ApplicationFiled: May 21, 2015Publication date: January 14, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Kazumasa TANIDA, Takamitsu YOSHIDA, Kuniaki UTSUMI, Atsuko KAWASAKI
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Publication number: 20150348862Abstract: A semiconductor device (1,21) includes a solid state device (2,22), a semiconductor chip (3) that has a functional surface (3a) on which a functional element (4) is formed and that is bonded on a surface of the solid state device with the functional surface thereof facing the surface of the solid state device and while maintaining a predetermined distance between the functional surface thereof and the surface of the solid state device, an insulating film (6) that is provided on the surface (2a, 22a) of the solid state device facing the semiconductor chip and that has an opening (6a) greater in size than the semiconductor chip when the surface of the solid state device facing the semiconductor chip is vertically viewed down in plane, and a sealing layer (7) that seals a space between the solid state device and the semiconductor chip.Type: ApplicationFiled: August 12, 2015Publication date: December 3, 2015Applicant: ROHM CO., LTD.Inventors: Kazumasa Tanida, Osamu Miyata
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Patent number: 9165962Abstract: A solid state imaging device includes a semiconductor layer, and a light shielding portion. The semiconductor layer has multiple photoelectric conversion elements. The light shielding portion is provided in the semiconductor layer, and has a light shielding member whose interface with the semiconductor layer is covered by an insulating film. The light shielding portion includes a light shielding region and an element isolation region. The light shielding region is provided in the semiconductor layer on the side close to the light receiving surface of the photoelectric conversion element for shielding light incident on the photoelectric conversion element from a specific direction. The element isolation region is formed to project in the depth direction of the semiconductor layer from the light shielding region toward a portion between the multiple photoelectric conversion elements in order to electrically and optically isolate the multiple photoelectric conversion elements from one another.Type: GrantFiled: December 2, 2013Date of Patent: October 20, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Kazumasa Tanida
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Patent number: 9117774Abstract: A semiconductor device (1,21) includes a solid state device (2,22), a semiconductor chip (3) that has a functional surface (3a) on which a functional element (4) is formed and that is bonded on a surface of the solid state device with the functional surface thereof facing the surface of the solid state device and while maintaining a predetermined distance between the functional surface thereof and the surface of the solid state device, an insulating film (6) that is provided on the surface (2a, 22a) of the solid state device facing the semiconductor chip and that has an opening (6a) greater in size than the semiconductor chip when the surface of the solid state device facing the semiconductor chip is vertically viewed down in plane, and a sealing layer (7) that seals a space between the solid state device and the semiconductor chip.Type: GrantFiled: May 13, 2014Date of Patent: August 25, 2015Assignee: ROHM CO., LTD.Inventors: Kazumasa Tanida, Osamu Miyata
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Patent number: 9004337Abstract: According to one embodiment, a system for manufacturing a semiconductor device includes a spontaneous joining unit and a deformative joining unit. The spontaneous joining unit overlaps a first substrate and a second substrate and spontaneously joins mutual center portions of respective joint faces of the first substrate and the second substrate. The deformative joining unit deforms at least one peripheral portion of the respective joint faces of the first substrate and second substrate joined by the spontaneous joining unit toward the other peripheral portion and joins the mutual peripheral portions of the respective joint faces.Type: GrantFiled: May 24, 2012Date of Patent: April 14, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Hongo, Kenji Takahashi, Kazumasa Tanida
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Patent number: 8980671Abstract: A manufacturing method of a semiconductor device according to embodiments includes forming a photodiode layer, which is an active region including a photodiode, on a main surface of a first substrate, forming a wiring layer, which includes a wire and a dielectric layer covering the wire, on the photodiode layer, and forming a dielectric film on the wiring layer. The manufacturing method of the semiconductor device according to the embodiments further includes bonding a second substrate to the dielectric film of the first substrate so that a crystal orientation of the photodiode layer matches a crystal orientation of the second substrate.Type: GrantFiled: February 8, 2012Date of Patent: March 17, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Hongo, Kazumasa Tanida, Akihiro Hori, Kenji Takahashi, Hideo Numata
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Publication number: 20150035100Abstract: A solid state imaging device includes a semiconductor layer, and a light shielding portion. The semiconductor layer has multiple photoelectric conversion elements. The light shielding portion is provided in the semiconductor layer, and has a light shielding member whose interface with the semiconductor layer is covered by an insulating film. The light shielding portion includes a light shielding region and an element isolation region. The light shielding region is provided in the semiconductor layer on the side close to the light receiving surface of the photoelectric conversion element for shielding light incident on the photoelectric conversion element from a specific direction. The element isolation region is formed to project in the depth direction of the semiconductor layer from the light shielding region toward a portion between the multiple photoelectric conversion elements in order to electrically and optically isolate the multiple photoelectric conversion elements from one another.Type: ApplicationFiled: December 2, 2013Publication date: February 5, 2015Applicant: Kabushiki Kaisha ToshibaInventor: Kazumasa TANIDA
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Publication number: 20140246789Abstract: A semiconductor device (1,21) includes a solid state device (2,22), a semiconductor chip (3) that has a functional surface (3a) on which a functional element (4) is formed and that is bonded on a surface of the solid state device with the functional surface thereof facing the surface of the solid state device and while maintaining a predetermined distance between the functional surface thereof and the surface of the solid state device, an insulating film (6) that is provided on the surface (2a, 22a) of the solid state device facing the semiconductor chip and that has an opening (6a) greater in size than the semiconductor chip when the surface of the solid state device facing the semiconductor chip is vertically viewed down in plane, and a sealing layer (7) that seals a space between the solid state device and the semiconductor chip.Type: ApplicationFiled: May 13, 2014Publication date: September 4, 2014Applicant: ROHM CO., LTD.Inventors: Kazumasa TANIDA, Osamu MIYATA
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Patent number: 8822307Abstract: According to one embodiment, a semiconductor manufacturing apparatus is provided. The semiconductor manufacturing apparatus includes a stage, a substrate supporter, first and second pushers, and a controller. The stage is configured to support outer periphery portions of the first semiconductor substrate from below. The substrate supporter is configured to hold the back of the second semiconductor substrate. The first and second pushers are configured to bring the first and second semiconductor substrates in contact. The controller is configured to form the bonding initiation point between the first and second semiconductor substrates.Type: GrantFiled: March 16, 2012Date of Patent: September 2, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Naoko Yamaguchi, Kazumasa Tanida, Hideo Numata, Satoshi Hongo, Kenji Takahashi
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Patent number: 8778778Abstract: According to an embodiment, an active layer is formed on a first surface of a semiconductor substrate, a wiring layer is formed on the active layer, and an insulating layer is formed covering the wiring layer. The first surface of the semiconductor substrate is bonded to a support substrate via the insulating layer, and the semiconductor substrate bonded to the support substrate is thinned leaving the semiconductor substrate having a predetermined thickness which covers the active layer from a second surface. At least a part of area of the thinned semiconductor substrate is removed to expose the active layer.Type: GrantFiled: August 18, 2011Date of Patent: July 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kazumasa Tanida, Masahiro Sekiguchi, Masayuki Dohi, Tsuyoshi Matsumura, Hideo Numata, Mari Otsuka, Naoko Yamaguchi, Takashi Shirono, Satoshi Hongo
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Patent number: 8754535Abstract: A semiconductor device (1,21) includes a solid state device (2,22), a semiconductor chip (3) that has a functional surface (3a) on which a functional element (4) is formed and that is bonded on a surface of the solid state device with the functional surface thereof facing the surface of the solid state device and while maintaining a predetermined distance between the functional surface thereof and the surface of the solid state device, an insulating film (6) that is provided on the surface (2a, 22a) of the solid state device facing the semiconductor chip and that has an opening (6a) greater in size than the semiconductor chip when the surface of the solid state device facing the semiconductor chip is vertically viewed down in plane, and a sealing layer (7) that seals a space between the solid state device and the semiconductor chip.Type: GrantFiled: March 1, 2013Date of Patent: June 17, 2014Assignee: Rohm Co., Ltd.Inventors: Kazumasa Tanida, Osamu Miyata
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Patent number: 8748316Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes polishing a peripheral portion of the semiconductor substrate, and forming a protective film to be an insulating film, on a surface of the semiconductor substrate including a surface exposed by the polishing.Type: GrantFiled: June 27, 2011Date of Patent: June 10, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Shirono, Mie Matsuo, Hideo Numata, Kazumasa Tanida, Tsuyoshi Matsumura
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Patent number: 8704337Abstract: In one embodiment, a method for manufacturing a semiconductor device includes following steps. An aperture is formed in an interlayer insulating film formed on a semiconductor wafer apart from an integrated circuit portion by etching process. The interlayer insulating film has a dielectric constant smaller than a silicon oxide film (SiO2), and the width of the aperture is larger than a dicing region. A resin layer is embedded in the aperture. An adhesive layer is formed on the interlayer insulating film and the resin layer. The semiconductor wafer is attached to a glass substrate using the adhesive layer by Face Down method. The semiconductor wafer, the resin layer, and the adhesive layer on a dicing region are cut by blade dicing. The semiconductor wafer and the glass substrate adhered to the semiconductor wafer are cut into pieces by the blade dicing of the glass substrate under the dicing region.Type: GrantFiled: September 13, 2010Date of Patent: April 22, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Eiji Takano, Hideo Numata, Kazumasa Tanida
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Patent number: 8609511Abstract: According to one embodiment, an insulation film is formed over the surface, backside, and sides of a first substrate. Next, the insulation film formed over the surface of the first substrate is removed. Then, a joining layer is formed over the surface of the first substrate, from which the insulation film has been removed. Subsequently, the first substrate is bonded to a second substrate via a joining layer.Type: GrantFiled: August 29, 2011Date of Patent: December 17, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Shirono, Kazumasa Tanida, Naoko Yamaguchi, Satoshi Hongo, Tsuyoshi Matsumura
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Patent number: 8552545Abstract: A manufacturing method for a semiconductor device includes: the step of preparing a semiconductor chip which is provided with a functional element formed on a front surface side of a semiconductor substrate, a feedthrough electrode which is placed within a through hole that penetrates the semiconductor substrate, a front surface side connection member which protrudes from the front surface, and a rear surface side connection member which has a joining surface within a recess that is formed in a rear surface; the step of preparing a solid-state device where a solid-state device side connection member for connection to the front surface side connection member is formed on one surface; and the joining step of making the front surface of the semiconductor chip face the first surface of the solid-state device by holding the rear surface of the semiconductor chip, and of joining the front surface side connection member to the solid-state device side connection member.Type: GrantFiled: March 22, 2005Date of Patent: October 8, 2013Assignees: Rohm Co., Ltd., Renesas Technology Corp.Inventors: Kazumasa Tanida, Mitsuo Umemoto, Yukiharu Akiyama
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Publication number: 20130183810Abstract: According to one embodiment, a system for manufacturing a semiconductor device includes a spontaneous joining unit and a deformative joining unit. The spontaneous joining unit overlaps a first substrate and a second substrate and spontaneously joins mutual center portions of respective joint faces of the first substrate and the second substrate. The deformative joining unit deforms at least one peripheral portion of the respective joint faces of the first substrate and second substrate joined by the spontaneous joining unit toward the other peripheral portion and joins the mutual peripheral portions of the respective joint faces.Type: ApplicationFiled: May 24, 2012Publication date: July 18, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Satoshi HONGO, Kenji Takahashi, Kazumasa Tanida
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Patent number: 8426977Abstract: A semiconductor apparatus includes, a semiconductor substrate having first and second main surfaces and a through hole connecting the first and second main surfaces; a first insulation layer arranged on the first main surface, and having an opening corresponding to the through hole; a first conductive layer arranged on the first insulation layer, and covering the through hole; a second insulation layer arranged on an inner wall of the through hole and the second surface; a second conductive layer arranged in the through hole and on the second insulation layer, the second conductive layer contacting the first conductive layer; and a filling member arranged on the second conductive layer in the through hole, and having a gap between the second conductive layer on the first main surface side.Type: GrantFiled: August 11, 2009Date of Patent: April 23, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kazumasa Tanida, Hideko Mukaida, Susumu Harada, Chiaki Takubo