Patents by Inventor Kazumasa Tanida

Kazumasa Tanida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110073983
    Abstract: According to an embodiment, there is provided a semiconductor device including a semiconductor substrate having a first surface on which an active layer having a light receiving portion is provided and a second surface to be a light receiving surface for the light receiving portion, a wiring layer provided on the active layer, an insulating layer provided to cover the wiring layer, and a supporting substrate joined to the semiconductor substrate via the insulating layer to face the first surface of the semiconductor substrate. A joined body of the semiconductor substrate and the supporting substrate includes an intercalated portion provided between its outer peripheral surface and the active surface. The intercalated portion is provided to penetrate the semiconductor substrate and the insulating layer from the second surface of the semiconductor substrate and to reach inside the supporting substrate.
    Type: Application
    Filed: September 16, 2010
    Publication date: March 31, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazumasa Tanida, Chiaki Takubo, Hideo Numata, Yoshihisa Imori
  • Patent number: 7888760
    Abstract: A solid state imaging device includes: an imaging device substrate with an imaging device section formed on a first major surface side thereof; a backside interconnect electrode provided on a second major surface side of the imaging device substrate and electrically connected to the imaging device section, the second major surface being on the opposite side of the first major surface; a circuit substrate provided with a circuit substrate electrode opposed to the second major surface; a connecting portion electrically connecting the backside interconnect electrode to the circuit substrate electrode; and a light shielding layer provided coplanar with the backside interconnect electrode or on the circuit substrate side of the backside interconnect electrode.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: February 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hitoshi Sugiyama, Atsuko Yamashita, Kazutaka Akiyama, Susumu Harada, Masahiro Sekiguchi, Masayuki Dohi, Kazumasa Tanida, Chiaki Takubo, Hiroshi Yoshikawa, Akihiro Hori
  • Patent number: 7888778
    Abstract: A semiconductor device includes a semiconductor substrate having a through hole. An active layer is formed on a first surface of the semiconductor substrate. An inner wall surface of the through hole, a bottom surface of the through hole closed by the active layer and a second surface of the semiconductor substrate are covered with an insulating layer. A first opening is formed in the insulating layer which is present on the bottom surface of the through hole. A second opening is formed in the insulating layer which is present on the second surface of the semiconductor substrate. A first wiring layer is formed from within the through hole onto the second surface of the semiconductor substrate. A second wiring layer is formed to connect to the second surface through the second opening.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: February 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Tanida, Masahiro Sekiguchi, Ninao Sato, Kenji Takahashi
  • Publication number: 20100252902
    Abstract: A semiconductor device, includes: a semiconductor substrate including a first surface and a second surface which are opposite to one another; a light receiving portion provided at the first surface of the semiconductor substrate; and an optical transparent protective member so as to cover and to be adjacent to the first surface or the second surface of the semiconductor substrate; wherein a plurality of depressed portions are formed at the optical transparent protective member so as to be opposite to the light receiving portion.
    Type: Application
    Filed: March 5, 2010
    Publication date: October 7, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazumasa Tanida, Kenji Takahashi
  • Patent number: 7808064
    Abstract: An imaging element is formed on the first main surface of a semiconductor substrate. An external terminal is formed on the second main surface of the semiconductor substrate. A through-hole electrode is formed in a through hole formed in the semiconductor substrate. A first electrode pad is formed on the through-hole electrode in the first main surface. An interlayer insulating film is formed on the first electrode pad and on the first main surface. A second electrode pad is formed on the interlayer insulating film. A passivation film is formed on the second electrode pad and the interlayer insulating film, and has an opening which exposes a portion of the second electrode pad. A contact plug is formed between the first and second electrode pads in a region which does not overlap the opening when viewed in a direction perpendicular to the surface of the semiconductor substrate.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: October 5, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Kawasaki, Mie Matsuo, Ikuko Inoue, Masayuki Ayabe, Masahiro Sekiguchi, Kazumasa Tanida
  • Publication number: 20100213564
    Abstract: A sensor chip includes: a semiconductor substrate that is provided with a light receiving portion on a main surface; a light transmissive member that is provided on the main surface of the semiconductor substrate, enclosing a hollow portion above the light receiving portion, to surround upper and periphery of the light receiving portion; and a light transmissive protective member that is provided on the light transmissive member.
    Type: Application
    Filed: September 10, 2009
    Publication date: August 26, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazumasa Tanida, Hideo Numata, Eiji Takano
  • Publication number: 20100038741
    Abstract: A semiconductor apparatus includes, a semiconductor substrate having first and second main surfaces and a thought hole connecting the first and second main surfaces; a first insulation layer arranged on the first main surface, and having an opening corresponding to the thought hole; a first conductive layer arranged on the first insulation layer, and covering the thought hole; a second insulation layer arranged on an inner wall of the thought hole and the second surface; a second conductive layer arranged in the thought hole and on the second insulation layer, the second conductive layer contacting the first conductive layer; and a filling member arranged on the second conductive layer in the through hole, and having a gap between the second conductive layer on the first main surface side.
    Type: Application
    Filed: August 11, 2009
    Publication date: February 18, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazumasa Tanida, Hideko Mukaida, Susumu Harada, Chiaki Takubo
  • Publication number: 20100025860
    Abstract: In one aspect of the present invention, a semiconductor device, may include a semiconductor substrate having a first surface and a second surface opposite to the first surface; a through hole in the semiconductor substrate, including an expansion portion which is provided in a vicinity of the first surface so that an opening area of the first opening is greater than an opening area of a lowermost portion of the expansion portion; a first insulating layer on the first surface of the semiconductor substrate; a first wiring layer on the first insulating layer to close the opening of the first insulating layer; a second insulating layer provided on the expansion portion of the through hole; and a second wiring layer on the second insulating layer to extend from inside of the through hole to the second surface of the semiconductor substrate.
    Type: Application
    Filed: July 31, 2009
    Publication date: February 4, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazumasa Tanida, Mie Matsuo, Masahiro Sekiguchi, Chiaki Takubo
  • Patent number: 7638421
    Abstract: A manufacturing method for a semiconductor device, including the steps of: forming a passivation film that covers a surface of a semiconductor substrate on which electrodes have been formed, in which an opening is formed so as to expose a predetermined electrode from among the electrodes; forming a diffusion prevention plug of a first metal in the vicinity of the opening in the passivation film; supplying a second metal material to the surface of the semiconductor substrate on which the diffusion prevention plug has been formed, so as to form a seed layer of the second metal; forming a resist film that covers the seed layer and in which an opening is formed so as to expose a predetermined region of the seed layer on the diffusion prevention plug; supplying a third metal material into the opening in the resist film so as to form a protrusion electrode of the third metal; removing the resist film after the step of forming a protrusion electrode; and removing the seed layer after the step of forming a protrusion
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: December 29, 2009
    Assignees: Rohm Co., Ltd., Renesas Technology Corp., Sanyo Electric Co., Ltd.
    Inventors: Kazumasa Tanida, Yoshihiko Nemoto, Mitsuo Umemoto
  • Publication number: 20090284631
    Abstract: A semiconductor package includes a solid-state imaging element, electrode pad, through-hole electrode, and light-transmitting substrate. The solid-state imaging element is formed on the first main surface of a semiconductor substrate. The electrode pad is formed on the first main surface of the semiconductor substrate. The through-hole electrode is formed to extend through the semiconductor substrate between the first main surface and a second main surface opposite to the electrode pad formed on the first main surface. The light-transmitting substrate is placed on a patterned adhesive to form a hollow on the solid-state imaging element. The thickness of the semiconductor substrate below the hollow when viewed from the light-transmitting substrate is larger than that of the semiconductor substrate below the adhesive.
    Type: Application
    Filed: July 29, 2009
    Publication date: November 19, 2009
    Inventors: Mie MATSUO, Atsuko Kawasaki, Kenji Takahashi, Masahiro Sekiguchi, Kazumasa Tanida
  • Publication number: 20090283847
    Abstract: An imaging element is formed on the first main surface of a semiconductor substrate. An external terminal is formed on the second main surface of the semiconductor substrate. A through-hole electrode is formed in a through hole formed in the semiconductor substrate. A first electrode pad is formed on the through-hole electrode in the first main surface. An interlayer insulating film is formed on the first electrode pad and on the first main surface. A second electrode pad is formed on the interlayer insulating film. A passivation film is formed on the second electrode pad and the interlayer insulating film, and has an opening which exposes a portion of the second electrode pad. A contact plug is formed between the first and second electrode pads in a region which does not overlap the opening when viewed in a direction perpendicular to the surface of the semiconductor substrate.
    Type: Application
    Filed: July 23, 2009
    Publication date: November 19, 2009
    Inventors: Atsuko KAWASAKI, Mie Matsuo, Ikuko Inoue, Masayuki Ayabe, Masahiro Sekiguchi, Kazumasa Tanida
  • Patent number: 7598613
    Abstract: A semiconductor device is provided with: a solid device having a connection surface formed with a connection electrode projected therefrom; a semiconductor chip which has a functional surface formed with a metal bump projected therefrom and which is bonded to the connection surface of the solid device as directing its functional surface to the connection surface and maintaining a predetermined distance between the functional surface and the connection surface; and a connecting member containing a low melting point metal having a lower solidus temperature than that of the connection electrode and the bump, and interconnecting the connection electrode and the bump. A sum of a height of the connection electrode and a height of the bump is not less than a half of the predetermined distance.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: October 6, 2009
    Assignee: Rohm Co., Ltd.
    Inventors: Kazumasa Tanida, Osamu Miyata
  • Publication number: 20090096051
    Abstract: A solid state imaging device includes: an imaging device substrate with an imaging device section formed on a first major surface side thereof; a backside interconnect electrode provided on a second major surface side of the imaging device substrate and electrically connected to the imaging device section, the second major surface being on the opposite side of the first major surface; a circuit substrate provided with a circuit substrate electrode opposed to the second major surface; a connecting portion electrically connecting the backside interconnect electrode to the circuit substrate electrode; and a light shielding layer provided coplanar with the backside interconnect electrode or on the circuit substrate side of the backside interconnect electrode.
    Type: Application
    Filed: October 10, 2008
    Publication date: April 16, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hitoshi SUGIYAMA, Atsuko Yamashita, Kazutaka Akiyama, Susumu Harada, Masahiro Sekiguchi, Masayuki Dohi, Kazumasa Tanida, Chiaki Takubo, Hiroshi Yoshikawa, Akihiro Hori
  • Publication number: 20090079020
    Abstract: A semiconductor device includes a semiconductor substrate having a first surface in which a light-receiving portion and electrodes are provided. The semiconductor substrate has a penetrating wiring layer connecting the first surface and the second surface. A light-transmissive protective member is disposed on the semiconductor substrate so as to cover the first surface. A gap is provided between the semiconductor substrate and the light-transmissive protective member. A protective film is formed at a surface of the light-transmissive protective member. The protective film has an opening provided at a region corresponding to the light-receiving portion.
    Type: Application
    Filed: September 18, 2008
    Publication date: March 26, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazumasa Tanida, Masahiro Sekiguchi, Susumu Harada
  • Publication number: 20090065906
    Abstract: A semiconductor device includes a semiconductor substrate having a through hole. An active layer is formed on a first surface of the semiconductor substrate. An inner wall surface of the through hole, a bottom surface of the through hole closed by the active layer and a second surface of the semiconductor substrate are covered with an insulating layer. A first opening is formed in the insulating layer which is present on the bottom surface of the through hole. A second opening is formed in the insulating layer which is present on the second surface of the semiconductor substrate. A first wiring layer is formed from within the through hole onto the second surface of the semiconductor substrate. A second wiring layer is formed to connect to the second surface through the second opening.
    Type: Application
    Filed: September 9, 2008
    Publication date: March 12, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazumasa Tanida, Masahiro Sekiguchi, Ninao Sato, Kenji Takahashi
  • Publication number: 20090057844
    Abstract: A semiconductor device 1 comprises a semiconductor substrate 2 having a through hole 3. A first insulation layer 4 having an opening 4a equal in diameter to the through hole 3 covers a front surface of the semiconductor substrate 2, and a first wiring layer 5 is formed thereon to cover the opening 4a. Further, a second insulation layer 6 is formed in the through hole 3 and on a rear surface of the semiconductor substrate 2. The second insulation layer 6 is formed to be in contact with an inner side of the first wiring layer 5 and has, in its contact portion, a plurality of small openings 6a smaller in diameter than the opening 4 of the first insulation layer 4. Further, a second wiring layer 7 is formed to fill the inside of the through hole 3, and the second wiring layer 7 is in contact with the inner side of the first wiring layer 5 via the small openings 6a of the second insulation layer 6.
    Type: Application
    Filed: September 3, 2008
    Publication date: March 5, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazumasa Tanida, Masahiro Sekiguchi
  • Publication number: 20080303170
    Abstract: A semiconductor device 1 has a through hole 3 formed in a second substrate 2. On the front surface of the semiconductor substrate 2, a first insulating layer 4 is coated having an opening 4a of the same diameter as that of the through hole 3, and a first wiring layer 5 is formed on the first insulating layer 4. Further, near the first wiring layer 5, the through hole 3 and a through connection portion constituted of a third insulating layer 8 formed on the inner surface and the like and a third wiring layer 9 filled and formed in the through hole 3 are formed. In addition, a second wiring layer 7 internally contacting the through connection portion is electrically connected with the first wiring layer 5. Between the inner surface of the through hole 3 and the first wiring layer 5, a second insulating layer 6 intervenes so that the first wiring layer 5 is separated from the third wiring layer 9 filled and formed in the through hole 3.
    Type: Application
    Filed: June 6, 2008
    Publication date: December 11, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazumasa TANIDA, Masahiro SEKIGUCHI, Kenji TAKAHASHI
  • Patent number: 7456502
    Abstract: The invention provides a wiring board (2,15) to which a semiconductor chip (3) is to be bonded while directing a surface of the semiconductor chip toward the wiring board. The wiring board includes a connection electrode (14) that is formed on a bonding surface (2a, 15a) to which the semiconductor chip is to be bonded and that is used to make a connection with the semiconductor chip, an insulating film (6) that is formed on the bonding surface and that has an opening (6a) to expose the connection electrode, and a low-melting-point metallic part (16) that is provided on the connection electrode in the opening and that is made of a low-melting-point metallic material whose solidus temperature is lower than that of the connection electrode.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: November 25, 2008
    Assignee: Rohm Co., Ltd.
    Inventors: Kazumasa Tanida, Osamu Miyata
  • Patent number: 7452751
    Abstract: Semiconductor device includes a pair of substrates (1, 2) disposed oppositely, semiconductor elements (5, 6) formed in the substrates (1, 2), respectively, and having semiconductor circuits (3, 4) and electrodes (7, 8), respectively, a wiring conductor (9) interposed between the electrodes (7, 8), and a through electrode (12) extending through one substrate (1) and connected to the electrode (7) via the wiring conductor (9). The other substrate (2) is disposed laterally of the through electrode (12). Surface of the through electrode (12) projecting from the one substrate (1) and lateral surface of the element (6) are coated with an insulation material (13). The through electrode (12) has one end exposed in a back surface of the one substrate (1), while other end is positioned flush with a back surface of the other substrate (2), being exposed.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: November 18, 2008
    Assignees: Renesas Technology Corp., Kabushiki Kaisha Toshiba, Rohm Co., Ltd.
    Inventors: Yoshihiko Nemoto, Kazumasa Tanida, Kenji Takahashi
  • Publication number: 20080246163
    Abstract: A semiconductor device (1,21) includes a solid state device (2,22), a semiconductor chip (3) that has a functional surface (3a) on which a functional element (4) is formed and that is bonded on a surface of the solid state device with the functional surface thereof facing the surface of the solid state device and while maintaining a predetermined distance between the functional surface thereof and the surface of the solid state device, an insulating film (6) that is provided on the surface (2a, 22a) of the solid state device facing the semiconductor chip and that has an opening (6a) greater in size than the semiconductor chip when the surface of the solid state device facing the semiconductor chip is vertically viewed down in plane, and a sealing layer (7) that seals a space between the solid state device and the semiconductor chip.
    Type: Application
    Filed: July 21, 2005
    Publication date: October 9, 2008
    Inventors: Kazumasa Tanida, Osamu Miyata