Patents by Inventor Kazumasa Tanida

Kazumasa Tanida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8405227
    Abstract: A semiconductor device (1,21) includes a solid state device (2,22), a semiconductor chip (3) that has a functional surface (3a) on which a functional element (4) is formed and that is bonded on a surface of the solid state device with the functional surface thereof facing the surface of the solid state device and while maintaining a predetermined distance between the functional surface thereof and the surface of the solid state device, an insulating film (6) that is provided on the surface (2a, 22a) of the solid state device facing the semiconductor chip and that has an opening (6a) greater in size than the semiconductor chip when the surface of the solid state device facing the semiconductor chip is vertically viewed down in plane, and a sealing layer (7) that seals a space between the solid state device and the semiconductor chip.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: March 26, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Kazumasa Tanida, Osamu Miyata
  • Patent number: 8404586
    Abstract: A manufacturing method for a semiconductor device includes: the step of preparing a semiconductor chip which is provided with a functional element formed on a front surface side of a semiconductor substrate, a feedthrough electrode which is placed within a through hole that penetrates the semiconductor substrate, a front surface side connection member which protrudes from the front surface, and a rear surface side connection member which has a joining surface within a recess that is formed in a rear surface; the step of preparing a solid state device where a solid state device side connection member for connection to the front surface side connection member is formed on one surface; and the joining step of making the front surface of the semiconductor chip face the first surface of the solid state device by holding the rear surface of the semiconductor chip, and of joining the front surface side connection member to the solid state device side connection member.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: March 26, 2013
    Assignees: Rohm Co., Ltd., Sanyo Electric Co., Ltd., Renesas Technology Corp.
    Inventors: Kazumasa Tanida, Mitsuo Umemoto, Yukiharu Akiyama
  • Publication number: 20130062737
    Abstract: According to one embodiment, a semiconductor device comprises a device substrate, and a supporting substrate. The supporting substrate is joined onto the device substrate. The device substrate has a first groove in an outer circumferential portion on a joint surface side to the supporting substrate.
    Type: Application
    Filed: March 23, 2012
    Publication date: March 14, 2013
    Inventors: Satoshi HONGO, Kazumasa Tanida, Kenji Takahashi
  • Publication number: 20120329241
    Abstract: According to one embodiment, a semiconductor manufacturing apparatus is provided. The semiconductor manufacturing apparatus includes a stage, a substrate supporter, first and second pushers, and a controller. The stage is configured to support outer periphery portions of the first semiconductor substrate from below. The substrate supporter is configured to hold the back of the second semiconductor substrate. The first and second pushers are configured to bring the first and second semiconductor substrates in contact. The controller is configured to form the bonding initiation point between the first and second semiconductor substrates.
    Type: Application
    Filed: March 16, 2012
    Publication date: December 27, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Naoko Yamaguchi, Kazumasa Tanida, Hideo Numata, Satoshi Hongo, Kenji Takahashi
  • Patent number: 8338904
    Abstract: According to an embodiment, there is provided a semiconductor device including a semiconductor substrate having a first surface on which an active layer having a light receiving portion is provided and a second surface to be a light receiving surface for the light receiving portion, a wiring layer provided on the active layer, an insulating layer provided to cover the wiring layer, and a supporting substrate joined to the semiconductor substrate via the insulating layer to face the first surface of the semiconductor substrate. A joined body of the semiconductor substrate and the supporting substrate includes an intercalated portion provided between its outer peripheral surface and the active surface. The intercalated portion is provided to penetrate the semiconductor substrate and the insulating layer from the second surface of the semiconductor substrate and to reach inside the supporting substrate.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Tanida, Chiaki Takubo, Hideo Numata, Yoshihisa Imori
  • Patent number: 8309430
    Abstract: According to one embodiment, a first substrate and a second substrate are pressed from an opposite surface of a joint surface of the second substrate such that a joint surface of the first substrate and the joint surface of the second substrate are in contact with each other. The second substrate is restrained by a member to provide a gap between the joint surfaces. It is determined, based on a temporal change of a joint interface calculated based on an image imaged from the opposite surface side of the joint surface, whether joining is normally performed.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: November 13, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Tanida, Naoko Yamaguchi, Satoshi Hongo, Chiaki Takubo, Hideo Numata
  • Patent number: 8269315
    Abstract: A semiconductor device 1 has a through hole 3 formed in a second substrate 2. On the front surface of the semiconductor substrate 2, a first insulating layer 4 is coated having an opening 4a of the same diameter as that of the through hole 3, and a first wiring layer 5 is formed on the first insulating layer 4. Further, near the first wiring layer 5, the through hole 3 and a through connection portion constituted of a third insulating layer 8 formed on the inner surface and the like and a third wiring layer 9 filled and formed in the through hole 3 are formed. In addition, a second wiring layer 7 internally contacting the through connection portion is electrically connected with the first wiring layer 5. Between the inner surface of the through hole 3 and the first wiring layer 5, a second insulating layer 6 intervenes so that the first wiring layer 5 is separated from the third wiring layer 9 filled and formed in the through hole 3.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: September 18, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Tanida, Masahiro Sekiguchi, Kenji Takahashi
  • Publication number: 20120217600
    Abstract: A manufacturing method of a semiconductor device according to embodiments includes forming a photodiode layer, which is an active region including a photodiode, on a main surface of a first substrate, forming a wiring layer, which includes a wire and a dielectric layer covering the wire, on the photodiode layer, and forming a dielectric film on the wiring layer. The manufacturing method of the semiconductor device according to the embodiments further includes bonding a second substrate to the dielectric film of the first substrate so that a crystal orientation of the photodiode layer matches a crystal orientation of the second substrate.
    Type: Application
    Filed: February 8, 2012
    Publication date: August 30, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoshi HONGO, Kazumasa Tanida, Akihiro Hori, Kenji Takahashi, Hideo Numata
  • Patent number: 8237285
    Abstract: Semiconductor device includes semiconductor substrate, through hole having first opening and second opening, and including an expansion portion so that an opening area of first opening is greater than an opening area of lowermost portion of expansion portion, first insulating layer, and having an opening which communicates with through hole and has an area smaller than opening area of first opening, first wiring layer provided on first insulating layer, second insulating layer provided on expansion portion of through hole, and to cover first opening and an inner wall surface of through hole, second insulating layer having an opening communicating with opening of first insulating layer so as to expose first wiring layer through opening of first insulating layer, and second wiring layer provided on second insulating layer to extend from inside of through hole, and being connected to first wiring layer via openings of first and second insulating layers.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: August 7, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Tanida, Mie Matsuo, Masahiro Sekiguchi, Chiaki Takubo
  • Publication number: 20120190138
    Abstract: According to one embodiment, semiconductor manufacturing apparatus includes a first member that holds a first semiconductor substrate; a second member that holds a second semiconductor substrate in a state where a bonding surface of the second semiconductor substrate faces a bonding surface of the first semiconductor substrate; a distance detecting unit that detects a distance between the bonding surface of the first semiconductor substrate and the bonding surface of the second semiconductor substrate; an adjusting unit that adjusts the distance between the bonding surface of the first semiconductor substrate and the bonding surface of the second semiconductor substrate to a predetermined value by moving at least one of the first and second members based on a detection result of the distance detecting unit; and a third member that forms the bonding start point between the first semiconductor substrate and the second semiconductor substrate.
    Type: Application
    Filed: January 20, 2012
    Publication date: July 26, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazumasa TANIDA, Satoshi Hongo, Naoko Yamaguchi, Kenji Takahashi, Hideo Numata
  • Patent number: 8228426
    Abstract: A semiconductor package includes a solid-state imaging element, electrode pad, through-hole electrode, and light-transmitting substrate. The solid-state imaging element is formed on the first main surface of a semiconductor substrate. The electrode pad is formed on the first main surface of the semiconductor substrate. The through-hole electrode is formed to extend through the semiconductor substrate between the first main surface and a second main surface opposite to the electrode pad formed on the first main surface. The light-transmitting substrate is placed on a patterned adhesive to form a hollow on the solid-state imaging element. The thickness of the semiconductor substrate below the hollow when viewed from the light-transmitting substrate is larger than that of the semiconductor substrate below the adhesive.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: July 24, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mie Matsuo, Atsuko Kawasaki, Kenji Takahashi, Masahiro Sekiguchi, Kazumasa Tanida
  • Publication number: 20120068290
    Abstract: According to one embodiment, an insulation film is formed over the surface, backside, and sides of a first substrate. Next, the insulation film formed over the surface of the first substrate is removed. Then, a joining layer is formed over the surface of the first substrate, from which the insulation film has been removed. Subsequently, the first substrate is bonded to a second substrate via a joining layer.
    Type: Application
    Filed: August 29, 2011
    Publication date: March 22, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takashi Shirono, Kazumasa Tanida, Naoko Yamaguchi, Satoshi Hongo, Tsuyoshi Matsumura
  • Publication number: 20120049312
    Abstract: According to an embodiment, an active layer is formed on a first surface of a semiconductor substrate, a wiring layer is formed on the active layer, and an insulating layer is formed covering the wiring layer. The first surface of the semiconductor substrate is bonded to a support substrate via the insulating layer, and the semiconductor substrate bonded to the support substrate is thinned leaving the semiconductor substrate having a predetermined thickness which covers the active layer from a second surface. At least a part of area of the thinned semiconductor substrate is removed to expose the active layer.
    Type: Application
    Filed: August 18, 2011
    Publication date: March 1, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazumasa TANIDA, Masahiro Sekiguchi, Masayuki Dohi, Tsuyoshi Matsumura, Hideo Numata, Mari Otsuka, Naoko Yamaguchi, Takashi Shirono, Satoshi Hongo
  • Patent number: 8089163
    Abstract: A semiconductor device production method including: the step of forming a stopper mask layer of a first metal on a semiconductor substrate, the stopper mask layer having an opening at a predetermined position thereof; the metal supplying step of supplying a second metal into the opening of the stopper mask layer to form a projection electrode of the second metal; and removing the stopper mask layer after the metal supplying step.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: January 3, 2012
    Assignees: Rohm Co., Ltd., Renesas Technology Corporation, Sanyo Electric Co., Ltd.
    Inventors: Kazumasa Tanida, Yoshihiko Nemoto, Mitsuo Umemoto
  • Publication number: 20110317050
    Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes polishing a peripheral portion of the semiconductor substrate, and forming a protective film to be an insulating film, on a surface of the semiconductor substrate including a surface exposed by the polishing.
    Type: Application
    Filed: June 27, 2011
    Publication date: December 29, 2011
    Inventors: Takashi Shirono, Mie Matsuo, Hideo Numata, Kazumasa Tanida, Tsuyoshi Matsumura
  • Publication number: 20110304003
    Abstract: According to the embodiments, a semiconductor substrate, an active layer that is formed on one surface of the semiconductor substrate, a wiring layer that is formed on the active layer and includes a wire to be a convex portion on a surface that is not in contact with the active layer, a insulation layer that is formed on the wiring layer to have a concave portion, an embedded layer that is provided on the concave portion of the insulation layer, a bonding layer that is provided on the insulation layer and the embedded layer, and a substrate that is bonded to the bonding layer to face one surface of the semiconductor substrate are included.
    Type: Application
    Filed: June 2, 2011
    Publication date: December 15, 2011
    Inventors: Kazumasa Tanida, Naoko Yamaguchi, Satoshi Hongo, Hideo Numata
  • Patent number: 8063462
    Abstract: A semiconductor device includes a semiconductor substrate having a first surface in which a light-receiving portion and electrodes are provided. The semiconductor substrate has a penetrating wiring layer connecting the first surface and the second surface. A light-transmissive protective member is disposed on the semiconductor substrate so as to cover the first surface. A gap is provided between the semiconductor substrate and the light-transmissive protective member. A protective film is formed at a surface of the light-transmissive protective member. The protective film has an opening provided at a region corresponding to the light-receiving portion.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: November 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Tanida, Masahiro Sekiguchi, Susumu Harada
  • Publication number: 20110217795
    Abstract: According to one embodiment, a first substrate and a second substrate are pressed from an opposite surface of a joint surface of the second substrate such that a joint surface of the first substrate and the joint surface of the second substrate are in contact with each other. The second substrate is restrained by a member to provide a gap between the joint surfaces. It is determined, based on a temporal change of a joint interface calculated based on an image imaged from the opposite surface side of the joint surface, whether joining is normally performed.
    Type: Application
    Filed: February 25, 2011
    Publication date: September 8, 2011
    Inventors: Kazumasa TANIDA, Naoko Yamaguchi, Satoshi Hongo, Chiaki Takubo, Hideo Numata
  • Patent number: 7928581
    Abstract: A manufacture method for semiconductor device (1, 21) including: a sealing-resin-layer forming step of forming a sealing resin layer (7) on a conductive member (13) formed at lest on one surface of a base substrate (11) formed with a plurality of wiring boards (2) therein, the conductive member spanning a boundary between a respective pair of adjoining wiring boards; and a step of moving the base substrate and a cutting tool (B) relative to each other in a manner to allow the cutting tool to pass through the base substrate from the other surface (2b) opposite from the one surface thereof toward the one surface thereof, thereby cutting the base substrate along the boundary between the respective pair of adjoining wiring boards.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: April 19, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Kazumasa Tanida, Osamu Miyata
  • Publication number: 20110073974
    Abstract: In one embodiment, a method for manufacturing a semiconductor device includes following steps. An aperture is formed in an interlayer insulating film formed on a semiconductor wafer apart from an integrated circuit portion by etching process. The interlayer insulating film has a dielectric constant smaller than a silicon oxide film (SiO2), and the width of the aperture is larger than a dicing region. A resin layer is embedded in the aperture. An adhesive layer is formed on the interlayer insulating film and the resin layer. The semiconductor wafer is attached to a glass substrate using the adhesive layer by Face Down method. The semiconductor wafer, the resin layer, and the adhesive layer on a dicing region are cut by blade dicing. The semiconductor wafer and the glass substrate adhered to the semiconductor wafer are cut into pieces by the blade dicing of the glass substrate under the dicing region.
    Type: Application
    Filed: September 13, 2010
    Publication date: March 31, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Eiji Takano, Hideo Numata, Kazumasa Tanida