Patents by Inventor Kazunobu Kuwazawa

Kazunobu Kuwazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200343288
    Abstract: A solid-state image sensor including: a first impurity region of a first conductivity type; a plurality of second impurity regions of a second conductivity type disposed in the first impurity region and arranged in a first direction; and a light shielding layer that overlaps the first impurity region and does not overlap the second impurity regions in a plan view, wherein the first impurity region has a first portion between adjacent ones of the second impurity regions, the light shielding layer has a second portion that overlaps the first portion in a plan view, and a length of the second portion in the first direction is smaller than a length of the first portion in the first direction.
    Type: Application
    Filed: April 23, 2020
    Publication date: October 29, 2020
    Inventors: Mitsuo SEKISAWA, Kazunobu KUWAZAWA
  • Publication number: 20200321239
    Abstract: A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.
    Type: Application
    Filed: June 19, 2020
    Publication date: October 8, 2020
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kazunobu KUWAZAWA, Shigeyuki SAKUMA, Hiroaki NITTA, Mitsuo SEKISAWA, Takehiro ENDO
  • Patent number: 10714375
    Abstract: A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: July 14, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kazunobu Kuwazawa, Shigeyuki Sakuma, Hiroaki Nitta, Mitsuo Sekisawa, Takehiro Endo
  • Patent number: 10541299
    Abstract: A semiconductor device includes a first conductivity type semiconductor substrate, a second conductivity type first and second buried diffusion layers that are arranged in the semiconductor substrate, a semiconductor layer arranged on the semiconductor substrate, a second conductivity type first impurity diffusion region that is arranged in the semiconductor layer, a second conductivity type second impurity diffusion region that is arranged, in the semiconductor layer, on the second buried diffusion layer, a second conductivity type first well that is arranged in a first region of the semiconductor layer, a first conductivity type second well that is arranged, in the semiconductor layer, in a second region, a first conductivity type third and fourth impurity diffusion regions that are arranged in the first well, and a first conductivity type fifth impurity diffusion region that is arranged in the second well.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: January 21, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kazunobu Kuwazawa, Shigeyuki Sakuma, Hiroaki Nitta, Mitsuo Sekisawa, Takehiro Endo
  • Patent number: 10347674
    Abstract: This solid-state image capturing device includes a light receiving element, a charge holding region, and a floating diffusion region that are arranged in a semiconductor substrate, and the light receiving element, a first transfer gate, and a second transfer gate in the semiconductor substrate, and is configured to have a potential gradient in the charge holding region such that signal charges that have been transferred from the light receiving element to the charge holding region by the first transfer gate are distributed more on the second transfer gate side than on the first transfer gate side.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: July 9, 2019
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kazunobu Kuwazawa, Noriyuki Nakamura, Mitsuo Sekisawa
  • Patent number: 10020333
    Abstract: In this solid-state imaging device, the sameness of the potential distributions in pixels, in a region from a photodiode of a transfer transistor to a floating diffusion in a charge transfer path, is improved. The solid-state imaging device includes a first transfer transistor including a first photodiode, a first gate electrode, and a first floating diffusion, a second transfer transistor including a second photodiode, a second gate electrode, and a second floating diffusion, a third transfer transistor including a third photodiode, a third gate electrode, and a third floating diffusion, and a reset transistor including a diffusion layer, which is a source or drain region, and a reset gate. The first to third floating diffusions and the diffusion layer of the reset transistor are separated from each other, and are electrically connected to each other via an interconnect. The first to third photodiodes are arrayed one-dimensionally.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: July 10, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kazunobu Kuwazawa, Noriyuki Nakamura, Mitsuo Sekisawa
  • Publication number: 20180083055
    Abstract: This solid-state image capturing device includes a light receiving element, a charge holding region, and a floating diffusion region that are arranged in a semiconductor substrate, and the light receiving element, a first transfer gate, and a second transfer gate in the semiconductor substrate, and is configured to have a potential gradient in the charge holding region such that signal charges that have been transferred from the light receiving element to the charge holding region by the first transfer gate are distributed more on the second transfer gate side than on the first transfer gate side.
    Type: Application
    Filed: September 20, 2017
    Publication date: March 22, 2018
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kazunobu KUWAZAWA, Noriyuki NAKAMURA, Mitsuo SEKISAWA
  • Publication number: 20180076251
    Abstract: A solid-state image capturing device includes: a pixel region including a light receiving element, a transfer gate, a floating diffusion region, and a buffer transistor; and an interconnect that is arranged in an N-th interconnect layer (N is an integer of two or more), and electrically connects the floating diffusion region and the buffer transistor.
    Type: Application
    Filed: September 8, 2017
    Publication date: March 15, 2018
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Noriyuki NAKAMURA, Kazunobu KUWAZAWA, Mitsuo SEKISAWA
  • Publication number: 20180076255
    Abstract: This solid-state image capturing device includes a light receiving element, a charge holding region, and a floating diffusion region that are arranged in a semiconductor substrate, a first transfer gate between the light receiving element and the charge holding region, a second transfer gate between the charge holding region and the floating diffusion region, an interconnect layer including an interconnect that is arranged on the semiconductor substrate via a plurality of interlayer insulating films, and a light shielding film that is arranged on the semiconductor substrate side relative to the interconnect layer and shields the charge holding region.
    Type: Application
    Filed: September 8, 2017
    Publication date: March 15, 2018
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kazunobu KUWAZAWA, Mitsuo SEKISAWA, Noriyuki NAKAMURA
  • Patent number: 9911814
    Abstract: A semiconductor device includes a P-type semiconductor substrate, a plurality of N-type buried diffusion layers that are arranged in the semiconductor substrate, an N-type first semiconductor layer that is arranged in a first region on a first buried diffusion layer, an N-type second semiconductor layer that is arranged in a second region on a second buried diffusion layer, an N-type first impurity diffusion region that surrounds the first region in plan view, a P-type second impurity diffusion region that is arranged in the second semiconductor layer, an N-type third impurity diffusion region that is arranged in the second semiconductor layer, an N-type fourth impurity diffusion region that is arranged in the first semiconductor layer. The second region is a region in which an N-type impurity diffusion region that has a higher impurity concentration than the second semiconductor layer cannot be arranged.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: March 6, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Hiroaki Nitta, Kazunobu Kuwazawa
  • Publication number: 20170330904
    Abstract: In this solid-state imaging device, the sameness of the potential distributions in pixels, in a region from a photodiode of a transfer transistor to a floating diffusion in a charge transfer path, is improved. The solid-state imaging device includes a first transfer transistor including a first photodiode, a first gate electrode, and a first floating diffusion, a second transfer transistor including a second photodiode, a second gate electrode, and a second floating diffusion, a third transfer transistor including a third photodiode, a third gate electrode, and a third floating diffusion, and a reset transistor including a diffusion layer, which is a source or drain region, and a reset gate. The first to third floating diffusions and the diffusion layer of the reset transistor are separated from each other, and are electrically connected to each other via an interconnect. The first to third photodiodes are arrayed one-dimensionally.
    Type: Application
    Filed: April 28, 2017
    Publication date: November 16, 2017
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kazunobu KUWAZAWA, Noriyuki NAKAMURA, Mitsuo SEKISAWA
  • Patent number: 9818790
    Abstract: A solid-state imaging device includes a P-well, a gate insulating film, a gate electrode, a P+-type pinning layer that is located in the P-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a P?-type impurity region that is located in the P-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an N?-type impurity region that is located in the P-well so as to extend under the pinning layer and the P?-type impurity region and be in contact with the P?-type impurity region and the gate insulating film, and an N+-type impurity region that is located in the P-well and includes a portion that is under a second end portion of the gate electrode.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: November 14, 2017
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kazunobu Kuwazawa, Noriyuki Nakamura, Mitsuo Sekisawa, Takehiro Endo
  • Patent number: 9818789
    Abstract: A solid-state imaging device includes a P-well, a gate insulating film, a gate electrode, a P+-type pinning layer that is located in the P-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a P?-type impurity region that is located in the P-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an N?-type impurity region that is in contact with the P?-type impurity region and the gate insulating film, and an N??-type impurity region that surrounds at least a portion of the N?-type impurity region in plan view.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: November 14, 2017
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kazunobu Kuwazawa, Noriyuki Nakamura, Mitsuo Sekisawa, Takehiro Endo
  • Patent number: 9786616
    Abstract: A semiconductor apparatus includes elements formed on a substrate, a first insulation layer, a first pad and a second pad arranged on the first insulation layer and located above the elements, and a second insulation layer that is arranged on the side surfaces and upper surfaces of the first pad and the second pad. The second insulation layer includes openings at upper surfaces of the first pad and the second pad. The thickness of the first pad and the second pad is 2 ?m or more, the thickness of the second insulation layer is less than or equal to ? of the thickness of the first pad and the second pad, and the distance between the first pad and the second pad is greater than or equal to four times the thickness of the first pad and the second pad.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: October 10, 2017
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kazunobu Kuwazawa, Hiroaki Nitta, Takehiro Endo, Mitsuo Sekisawa
  • Patent number: 9728566
    Abstract: A solid state imaging device according to the invention includes: a semiconductor layer of a first conductivity type; a gate insulation film that is located on the semiconductor layer; a gate electrode that is located on the gate insulation film; a first impurity region of a second conductivity type that is located at least in a region outside the gate electrode on a first end portion side; a second impurity region of the second conductivity type that is located in a region extending across a second end portion that is opposite to the first end portion of the gate electrode; and a third impurity region of the first conductivity type that is located on top of the second impurity region at a position outside the gate electrode on the second end portion side, and is in contact with the second impurity region.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: August 8, 2017
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Mitsuo Sekisawa, Kazunobu Kuwazawa, Noriyuki Nakamura, Takehiro Endo
  • Publication number: 20170179239
    Abstract: A semiconductor device includes a P-type semiconductor substrate, a plurality of N-type buried diffusion layers that are arranged in the semiconductor substrate, an N-type first semiconductor layer that is arranged in a first region on a first buried diffusion layer, an N-type second semiconductor layer that is arranged in a second region on a second buried diffusion layer, an N-type first impurity diffusion region that surrounds the first region in plan view, a P-type second impurity diffusion region that is arranged in the second semiconductor layer, an N-type third impurity diffusion region that is arranged in the second semiconductor layer, an N-type fourth impurity diffusion region that is arranged in the first semiconductor layer. The second region is a region in which an N-type impurity diffusion region that has a higher impurity concentration than the second semiconductor layer cannot be arranged.
    Type: Application
    Filed: December 5, 2016
    Publication date: June 22, 2017
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hiroaki NITTA, Kazunobu KUWAZAWA
  • Publication number: 20170170053
    Abstract: A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.
    Type: Application
    Filed: November 30, 2016
    Publication date: June 15, 2017
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kazunobu KUWAZAWA, Shigeyuki SAKUMA, Hiroaki NITTA, Mitsuo SEKISAWA, Takehiro ENDO
  • Publication number: 20170170262
    Abstract: A semiconductor device includes a first conductivity type semiconductor substrate, a second conductivity type first and second buried diffusion layers that are arranged in the semiconductor substrate, a semiconductor layer arranged on the semiconductor substrate, a second conductivity type first impurity diffusion region that is arranged in the semiconductor layer, a second conductivity type second impurity diffusion region that is arranged, in the semiconductor layer, on the second buried diffusion layer, a second conductivity type first well that is arranged in a first region of the semiconductor layer, a first conductivity type second well that is arranged, in the semiconductor layer, in a second region, a first conductivity type third and fourth impurity diffusion regions that are arranged in the first well, and a first conductivity type fifth impurity diffusion region that is arranged in the second well.
    Type: Application
    Filed: November 30, 2016
    Publication date: June 15, 2017
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kazunobu KUWAZAWA, Shigeyuki SAKUMA, Hiroaki NITTA, Mitsuo SEKISAWA, Takehiro ENDO
  • Publication number: 20170077156
    Abstract: A solid state imaging element according to the invention includes: a semiconductor layer of a first conductivity type; a gate insulation film on the semiconductor layer; a gate electrode on the gate insulation film; a first impurity region of a second conductivity type in the semiconductor layer and in a region outside the gate electrode on a first end portion side; a second impurity region of the second conductivity type in the semiconductor layer and in a region outside the gate electrode on a second end portion side that is opposite to the first end portion of the gate electrode; and a third impurity region of the first conductivity type over the second impurity region in the semiconductor layer at a position separate from the second end portion of the gate electrode as viewed in plan view, and is in contact with the second impurity region.
    Type: Application
    Filed: September 2, 2016
    Publication date: March 16, 2017
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Mitsuo SEKISAWA, Kazunobu KUWAZAWA, Noriyuki NAKAMURA, Takehiro ENDO
  • Publication number: 20170053880
    Abstract: A semiconductor apparatus includes elements formed on a substrate, a first insulation layer, a first pad and a second pad arranged on the first insulation layer and located above the elements, and a second insulation layer that is arranged on the side surfaces and upper surfaces of the first pad and the second pad. The second insulation layer includes openings at upper surfaces of the first pad and the second pad. The thickness of the first pad and the second pad is 2 ?m or more, the thickness of the second insulation layer is less than or equal to ? of the thickness of the first pad and the second pad, and the distance between the first pad and the second pad is greater than or equal to four times the thickness of the first pad and the second pad.
    Type: Application
    Filed: August 8, 2016
    Publication date: February 23, 2017
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kazunobu KUWAZAWA, Hiroaki NITTA, Takehiro ENDO, Mitsuo SEKISAWA