Abstract: An integrated circuit device is provided that has a split-gate type memory transistor, a first capacitor element and a second capacitor element formed on a common chip. The dielectric strength of each of the split-gate type memory transistor, the first capacitor element and the second capacitor element can be improved. An intermediate insulation film of the split-gate type memory transistor can include a thermal oxide film, an HTO film, a side-section insulation film, and another thermal oxide film. A dielectric film of the first capacitor element can include a thermal oxide film, an HTO film, and another thermal oxide film, while a dielectric film of the second capacitor element can include a thermal oxide film, an HTO film, a silicon nitride film, and another thermal oxide film.

Abstract: A semiconductor device comprises a memory cell array in which a plurality of nonvolatile semiconductor memory devices are arrayed in a row direction and a column direction. Each of the nonvolatile semiconductor memory devices includes a silicon semiconductor substrate, a floating gate disposed on the silicon semiconductor substrate through a gate insulating layer interposed therebetween, a second insulating layer disposed on the floating gate, and a control gate which is isolated from the floating gate and extends in the row direction. The nonvolatile semiconductor memory devices which are adjacent each other in the row direction are isolated by element isolation regions extending in the column direction. One of angles formed where a major axis direction of the floating gate in a planar configuration of the memory cell array intersects the column direction is an acute angle.