Patents by Inventor Kazunobu Kuwazawa

Kazunobu Kuwazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170025452
    Abstract: A solid state imaging device according to the invention includes: a semiconductor layer of a first conductivity type; a gate insulation film that is located on the semiconductor layer; a gate electrode that is located on the gate insulation film; a first impurity region of a second conductivity type that is located at least in a region outside the gate electrode on a first end portion side; a second impurity region of the second conductivity type that is located in a region extending across a second end portion that is opposite to the first end portion of the gate electrode; and a third impurity region of the first conductivity type that is located on top of the second impurity region at a position outside the gate electrode on the second end portion side, and is in contact with the second impurity region.
    Type: Application
    Filed: July 5, 2016
    Publication date: January 26, 2017
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Mitsuo SEKISAWA, Kazunobu KUWAZAWA, Noriyuki NAKAMURA, Takehiro ENDO
  • Patent number: 9520436
    Abstract: A solid-state imaging device includes a P-well, a gate insulating film, a gate electrode, a P+-type pinning layer that is located in the P-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a P?-type impurity region that is located in the P-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an N?-type impurity region that is located in the semiconductor layer under the P?-type impurity region and includes a portion that is under the pinning layer, and an N?-type impurity region that is in contact with the gate insulating film and the P?-type impurity region and is located so as to surround the N?-type impurity region in plan view.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: December 13, 2016
    Assignee: Dexerials Corporation
    Inventors: Kazunobu Kuwazawa, Noriyuki Nakamura, Mitsuo Sekisawa, Takehiro Endo
  • Publication number: 20160276389
    Abstract: A solid-state imaging device includes a P-well, a gate insulating film, a gate electrode, a P+-type pinning layer that is located in the P-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a P?-type impurity region that is located in the P-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an N?-type impurity region that is in contact with the P?-type impurity region and the gate insulating film, and an N??-type impurity region that surrounds at least a portion of the N?-type impurity region in plan view.
    Type: Application
    Filed: March 15, 2016
    Publication date: September 22, 2016
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kazunobu KUWAZAWA, Noriyuki NAKAMURA, Mitsuo SEKISAWA, Takehiro ENDO
  • Publication number: 20160276390
    Abstract: A solid-state imaging device includes a P-well, a gate insulating film, a gate electrode, a P+-type pinning layer that is located in the P-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a P?-type impurity region that is located in the P-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an N?-type impurity region that is located in the P-well so as to extend under the pinning layer and the P?-type impurity region and be in contact with the P?-type impurity region and the gate insulating film, and an N+-type impurity region that is located in the P-well and includes a portion that is under a second end portion of the gate electrode.
    Type: Application
    Filed: March 15, 2016
    Publication date: September 22, 2016
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kazunobu KUWAZAWA, Noriyuki NAKAMURA, Mitsuo SEKISAWA, Takehiro ENDO
  • Publication number: 20160276388
    Abstract: A solid-state imaging device includes a P-well, a gate insulating film, a gate electrode, a P+-type pinning layer that is located in the P-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a P?-type impurity region that is located in the P-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an N?-type impurity region that is located in the semiconductor layer under the P?-type impurity region and includes a portion that is under the pinning layer, and an N?-type impurity region that is in contact with the gate insulating film and the P?-type impurity region and is located so as to surround the N?-type impurity region in plan view.
    Type: Application
    Filed: March 14, 2016
    Publication date: September 22, 2016
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kazunobu KUWAZAWA, Noriyuki NAKAMURA, Mitsuo SEKISAWA, Takehiro ENDO
  • Patent number: 9425197
    Abstract: A semiconductor device includes a P-channel DMOS transistor provided with an N-type gate electrode, a P-channel MOS transistor provided with a P-type gate electrode, and an N-channel MOS transistor provided with an N-type gate electrode. The N-type gate electrode of the P-channel DMOS transistor desirably has a first end portion that is located on a source side of the P-channel DMOS transistor, a second end portion that is located on a drain side of the P-channel DMOS transistor, and a P-type diffusion layer at the first end portion.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: August 23, 2016
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Hiroaki Nitta, Hideyuki Akanuma, Kazunobu Kuwazawa
  • Publication number: 20150287726
    Abstract: A semiconductor device includes a P-channel DMOS transistor provided with an N-type gate electrode, a P-channel MOS transistor provided with a P-type gate electrode, and an N-channel MOS transistor provided with an N-type gate electrode. The N-type gate electrode of the P-channel DMOS transistor desirably has a first end portion that is located on a source side of the P-channel DMOS transistor, a second end portion that is located on a drain side of the P-channel DMOS transistor, and a P-type diffusion layer at the first end portion.
    Type: Application
    Filed: March 26, 2015
    Publication date: October 8, 2015
    Inventors: Hiroaki NITTA, Hideyuki AKANUMA, Kazunobu KUWAZAWA
  • Patent number: 9012991
    Abstract: A semiconductor device includes an N?-type well 13, a P-type body diffusion layer 14, an N+-type source diffusion layer 18, an N+-type drain diffusion layer 19, and a P+-type body contact region 32. A plurality of the P+-type body contact regions 32 are located along gate electrodes 17a and 17b, a plurality of first contact holes 25 are located along the gate electrodes, and a plurality of second contact holes 27 are located along the gate electrodes. The pitch of the plurality of P+-type body contact regions 32 is larger than the pitch of the plurality of first contact holes 25.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: April 21, 2015
    Assignee: Seiko Epson Corporation
    Inventor: Kazunobu Kuwazawa
  • Publication number: 20150035056
    Abstract: A semiconductor device includes an N?-type well 13, a P-type body diffusion layer 14, an N+-type source diffusion layer 18, an N+-type drain diffusion layer 19, and a P+-type body contact region 32. A plurality of the P+-type body contact regions 32 are located along gate electrodes 17a and 17b, a plurality of first contact holes 25 are located along the gate electrodes, and a plurality of second contact holes 27 are located along the gate electrodes. The pitch of the plurality of P+-type body contact regions 32 is larger than the pitch of the plurality of first contact holes 25.
    Type: Application
    Filed: August 1, 2014
    Publication date: February 5, 2015
    Inventor: Kazunobu KUWAZAWA
  • Patent number: 8860100
    Abstract: A solid-state imaging device includes: a first photodiode receiving light of a first color; a second photodiode that is arranged next to the first photodiode in a first direction and receives light of a second color; a third photodiode that is arranged next to the second photodiode in a second direction and receives light of the first color; a fourth photodiode that is arranged next to the third photodiode in the first direction and receives light of a third color; a first reset transistor for discharging a charge generated in the first photodiode and the second photodiode; and a second reset transistor for discharging a charge generated in the third photodiode and the fourth photodiode. The first photodiode and the third photodiode have a small difference in area.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: October 14, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Kazunobu Kuwazawa
  • Publication number: 20120146117
    Abstract: A solid-state imaging device includes: a first photodiode receiving light of a first color; a second photodiode that is arranged next to the first photodiode in a first direction and receives light of a second color; a third photodiode that is arranged next to the second photodiode in a second direction and receives light of the first color; a fourth photodiode that is arranged next to the third photodiode in the first direction and receives light of a third color; a first reset transistor for discharging a charge generated in the first photodiode and the second photodiode; and a second reset transistor for discharging a charge generated in the third photodiode and the fourth photodiode. The first photodiode and the third photodiode have a small difference in area.
    Type: Application
    Filed: December 5, 2011
    Publication date: June 14, 2012
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Kazunobu KUWAZAWA
  • Patent number: 8183657
    Abstract: A solid state imaging device, includes: a sensor cell array having a plurality of sensor cells arranged in a matrix on a substrate, each sensor cell including: a photoelectric transducer provided in the substrate and generating photo-generated electric charges according to an incident light; a transfer gate formed on the substrate with a gate insulating layer therebetween; a charge retention region formed under the gate insulating layer and storing the photo-generated electric charges that are transferred from the photoelectric transducer by applying a predetermined potential to the transfer gate; a buried layer formed between the charge retention region and the gate insulating layer; and a floating diffusion storing the photo-generated electric charges that are transferred from the charge retention region by applying a predetermined potential to the transfer gate.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: May 22, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Kazunobu Kuwazawa
  • Publication number: 20110192961
    Abstract: A solid state imaging device includes a P? well region 3 formed in an N? type layer 2 in a state in which the N? type layer remains in a surface layer of a semiconductor substrate, a photodiode having a light reception region that generates photocharges by light irradiation, a carrier pocket 6 in which the photocharges are accumulated, a P+ type high concentration diffusion layer 5 that discharges the photocharges accumulated in the carrier pocket, a modulation gate electrode that is formed over the carrier pocket through a gate dielectric film 1a, and a reset gate electrode 4a that is formed over a portion between the carrier pocket 6 and the P+ type high concentration diffusion layer 5 through a gate dielectric film 1b.
    Type: Application
    Filed: January 24, 2011
    Publication date: August 11, 2011
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Kazunobu KUWAZAWA
  • Patent number: 7847984
    Abstract: A line sensor, includes a plurality of pixels which is arranged linearly, the number of the plurality of pixels including the number depending on a resolution, a first pixel group which is provided to a center portion of the plurality of pixels arranged linearly and has a pixel pitch shorter than a length corresponding to a pixel pitch calculated from the resolution, and a second pixel group which is provided to each of both side portions of the center portion, and has a pixel pitch longer than the length corresponding to the pixel pitch calculated from the resolution.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: December 7, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Kazunobu Kuwazawa
  • Patent number: 7671402
    Abstract: A solid-state imaging device includes: a substrate; a photoelectric transducer that is provided within the substrate and generates light-generated charge in accordance with incident light; a floating diffusion that retains the light-generated charge generated from the photoelectric transducer; a transfer and retention unit that is provided between the photoelectric transducer and the floating diffusion for a purpose of controlling a transfer of the light-generated charge and has a charge-retaining region that can retain the light-generated charge generated from the photoelectric transducer; a reset unit that initializes a potential of the floating diffusion; an amplifying transistor that generates an output based on a potential of the floating diffusion; a selection transistor that selectively outputs an output of the amplifying transistor; and an excessive charge-discharging unit that discharges excessive electric charge generated from the photoelectric transducer.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: March 2, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Kazunobu Kuwazawa
  • Patent number: 7649165
    Abstract: An apparatus including: a photodiode including: a first conductivity substrate; a second conductivity PD-well on the substrate's first surface side; and a first conductivity collection well inside the PD-well; a modulation transistor including: a second conductivity TR-well connected with the PD-well, and a junction depth shallower than that of the PD-well; a first conductivity modulation well inside the TR-well, and connected with the collection well; a second conductivity source inside the modulation well, and including a region contacting the first surface; a gate electrode in a region partially covering the modulation well and enclosing the source; a gate insulation layer between the gate and the first surface; and a second conductivity drain partially sandwiching the gate and opposing the source, and including a region contacting the first surface; and a transfer transistor connected to modulation transistors in pixels between the source and a connected source line.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: January 19, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Yorito Sakano, Sanae Nishida, Kazunobu Kuwazawa, Tetsuo Tatsuda
  • Patent number: 7583306
    Abstract: A solid state imaging device, including: a plurality of storage wells which stores an optically generated charge that is generated at a photoelectric conversion region corresponding to an incident light, the plurality of storage wells being inside a substrate; wherein a plurality of the photoelectric conversion regions is arrayed on the substrate in a two dimensional matrix; a plurality of amplifiers each installed per every pair of the photoelectric conversion regions that are adjacent in one direction of the two dimensional matrix, outputting a pixel signal that corresponds to the optically generated charge retained in a floating diffusion region; a plurality of transfer controlling elements, a pair of which is installed in every pair of the photoelectric conversion regions, changing a potential barrier of an optically generated charge transfer route, the transfer route being between each of the storage wells in the pair of the photoelectric conversion regions and the corresponding floating diffusion region
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: September 1, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Kazunobu Kuwazawa
  • Patent number: 7557845
    Abstract: A solid state imaging device comprises a substrate, a photoelectric conversion element, an accumulation well, a modulation well, a modulation transistor, a transfer control element, and an unwanted electric charge discharging control element. The photoelectric conversion element generates photo-generated electric charges corresponding to incident light, which are accumulated in the accumulation well. The transfer control element changes a potential barrier between the accumulation well and the modulation well. The modulation transistor has a channel threshold voltage controlled by the electric charges stored in the modulation well and outputs a pixel signal corresponding to the electric charges. The unwanted electric charge discharging control element discharges the electric charges that overflow from the accumulation well through the unwanted electric charge discharging channel.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: July 7, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Kazunobu Kuwazawa
  • Patent number: 7488997
    Abstract: A solid-state imaging device including a plurality of unit pixels, each of which includes: a storage well for storing electric charge generated by a photoelectric transducer using incident light; a transferring unit, which is formed on a top surface of a substrate, for transferring the electric charge to a floating diffusion region; and an amplifier for outputting a pixel signal that is amplified based on the electric charge transferred to the floating diffusion region, wherein: the transferring unit is a transfer control element having: a transfer gate that is provided on the substrate surface through an insulation film so that part of the transfer gate overlaps the storage well when the substrate is viewed from a direction orthogonal to the substrate surface; and an electric charge-retaining region for retaining the electric charge that is provided within the substrate and under the transfer gate; and further a diffusion layer that serves as a transfer path between the floating diffusion region and the elec
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: February 10, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Kazunobu Kuwazawa
  • Publication number: 20090014628
    Abstract: An apparatus including: a photodiode including: a first conductivity substrate; a second conductivity PD-well on the substrate's first surface side; and a first conductivity collection well inside the PD-well; a modulation transistor including: a second conductivity TR-well connected with the PD-well, and a junction depth shallower than that of the PD-well; a first conductivity modulation well inside the TR-well, and connected with the collection well; a second conductivity source inside the modulation well, and including a region contacting the first surface; a gate electrode in a region partially covering the modulation well and enclosing the source; a gate insulation layer between the gate and the first surface; and a second conductivity drain partially sandwiching the gate and opposing the source, and including a region contacting the first surface; and a transfer transistor connected to modulation transistors in pixels between the source and a connected source line.
    Type: Application
    Filed: March 21, 2008
    Publication date: January 15, 2009
    Applicant: Seiko Epson Corporation
    Inventors: Yorito Sakano, Sanae Nishida, Kazunobu Kuwazawa, Tetsuo Tatsuda