Abstract: A solid state imaging element according to the invention includes: a semiconductor layer of a first conductivity type; a gate insulation film on the semiconductor layer; a gate electrode on the gate insulation film; a first impurity region of a second conductivity type in the semiconductor layer and in a region outside the gate electrode on a first end portion side; a second impurity region of the second conductivity type in the semiconductor layer and in a region outside the gate electrode on a second end portion side that is opposite to the first end portion of the gate electrode; and a third impurity region of the first conductivity type over the second impurity region in the semiconductor layer at a position separate from the second end portion of the gate electrode as viewed in plan view, and is in contact with the second impurity region.

Abstract: A semiconductor apparatus includes elements formed on a substrate, a first insulation layer, a first pad and a second pad arranged on the first insulation layer and located above the elements, and a second insulation layer that is arranged on the side surfaces and upper surfaces of the first pad and the second pad. The second insulation layer includes openings at upper surfaces of the first pad and the second pad. The thickness of the first pad and the second pad is 2 ?m or more, the thickness of the second insulation layer is less than or equal to ? of the thickness of the first pad and the second pad, and the distance between the first pad and the second pad is greater than or equal to four times the thickness of the first pad and the second pad.

Abstract: A solid state imaging device according to the invention includes: a semiconductor layer of a first conductivity type; a gate insulation film that is located on the semiconductor layer; a gate electrode that is located on the gate insulation film; a first impurity region of a second conductivity type that is located at least in a region outside the gate electrode on a first end portion side; a second impurity region of the second conductivity type that is located in a region extending across a second end portion that is opposite to the first end portion of the gate electrode; and a third impurity region of the first conductivity type that is located on top of the second impurity region at a position outside the gate electrode on the second end portion side, and is in contact with the second impurity region.

Abstract: A solid-state imaging device includes a P-well, a gate insulating film, a gate electrode, a P+-type pinning layer that is located in the P-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a P?-type impurity region that is located in the P-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an N?-type impurity region that is located in the semiconductor layer under the P?-type impurity region and includes a portion that is under the pinning layer, and an N?-type impurity region that is in contact with the gate insulating film and the P?-type impurity region and is located so as to surround the N?-type impurity region in plan view.

Abstract: A solid-state imaging device includes a P-well, a gate insulating film, a gate electrode, a P+-type pinning layer that is located in the P-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a P?-type impurity region that is located in the P-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an N?-type impurity region that is located in the semiconductor layer under the P?-type impurity region and includes a portion that is under the pinning layer, and an N?-type impurity region that is in contact with the gate insulating film and the P?-type impurity region and is located so as to surround the N?-type impurity region in plan view.

Abstract: A solid-state imaging device includes a P-well, a gate insulating film, a gate electrode, a P+-type pinning layer that is located in the P-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a P?-type impurity region that is located in the P-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an N?-type impurity region that is located in the P-well so as to extend under the pinning layer and the P?-type impurity region and be in contact with the P?-type impurity region and the gate insulating film, and an N+-type impurity region that is located in the P-well and includes a portion that is under a second end portion of the gate electrode.

Abstract: A solid-state imaging device includes a P-well, a gate insulating film, a gate electrode, a P+-type pinning layer that is located in the P-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a P?-type impurity region that is located in the P-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an N?-type impurity region that is in contact with the P?-type impurity region and the gate insulating film, and an N??-type impurity region that surrounds at least a portion of the N?-type impurity region in plan view.

Abstract: A semiconductor device includes a P-channel DMOS transistor provided with an N-type gate electrode, a P-channel MOS transistor provided with a P-type gate electrode, and an N-channel MOS transistor provided with an N-type gate electrode. The N-type gate electrode of the P-channel DMOS transistor desirably has a first end portion that is located on a source side of the P-channel DMOS transistor, a second end portion that is located on a drain side of the P-channel DMOS transistor, and a P-type diffusion layer at the first end portion.

Abstract: A semiconductor device includes a P-channel DMOS transistor provided with an N-type gate electrode, a P-channel MOS transistor provided with a P-type gate electrode, and an N-channel MOS transistor provided with an N-type gate electrode. The N-type gate electrode of the P-channel DMOS transistor desirably has a first end portion that is located on a source side of the P-channel DMOS transistor, a second end portion that is located on a drain side of the P-channel DMOS transistor, and a P-type diffusion layer at the first end portion.

Abstract: A semiconductor device includes an N?-type well 13, a P-type body diffusion layer 14, an N+-type source diffusion layer 18, an N+-type drain diffusion layer 19, and a P+-type body contact region 32. A plurality of the P+-type body contact regions 32 are located along gate electrodes 17a and 17b, a plurality of first contact holes 25 are located along the gate electrodes, and a plurality of second contact holes 27 are located along the gate electrodes. The pitch of the plurality of P+-type body contact regions 32 is larger than the pitch of the plurality of first contact holes 25.

Abstract: A semiconductor device includes an N?-type well 13, a P-type body diffusion layer 14, an N+-type source diffusion layer 18, an N+-type drain diffusion layer 19, and a P+-type body contact region 32. A plurality of the P+-type body contact regions 32 are located along gate electrodes 17a and 17b, a plurality of first contact holes 25 are located along the gate electrodes, and a plurality of second contact holes 27 are located along the gate electrodes. The pitch of the plurality of P+-type body contact regions 32 is larger than the pitch of the plurality of first contact holes 25.

Abstract: A solid-state imaging device includes: a first photodiode receiving light of a first color; a second photodiode that is arranged next to the first photodiode in a first direction and receives light of a second color; a third photodiode that is arranged next to the second photodiode in a second direction and receives light of the first color; a fourth photodiode that is arranged next to the third photodiode in the first direction and receives light of a third color; a first reset transistor for discharging a charge generated in the first photodiode and the second photodiode; and a second reset transistor for discharging a charge generated in the third photodiode and the fourth photodiode. The first photodiode and the third photodiode have a small difference in area.

Abstract: A solid-state imaging device includes: a first photodiode receiving light of a first color; a second photodiode that is arranged next to the first photodiode in a first direction and receives light of a second color; a third photodiode that is arranged next to the second photodiode in a second direction and receives light of the first color; a fourth photodiode that is arranged next to the third photodiode in the first direction and receives light of a third color; a first reset transistor for discharging a charge generated in the first photodiode and the second photodiode; and a second reset transistor for discharging a charge generated in the third photodiode and the fourth photodiode. The first photodiode and the third photodiode have a small difference in area.

Abstract: A solid state imaging device, includes: a sensor cell array having a plurality of sensor cells arranged in a matrix on a substrate, each sensor cell including: a photoelectric transducer provided in the substrate and generating photo-generated electric charges according to an incident light; a transfer gate formed on the substrate with a gate insulating layer therebetween; a charge retention region formed under the gate insulating layer and storing the photo-generated electric charges that are transferred from the photoelectric transducer by applying a predetermined potential to the transfer gate; a buried layer formed between the charge retention region and the gate insulating layer; and a floating diffusion storing the photo-generated electric charges that are transferred from the charge retention region by applying a predetermined potential to the transfer gate.

Abstract: A solid state imaging device includes a P? well region 3 formed in an N? type layer 2 in a state in which the N? type layer remains in a surface layer of a semiconductor substrate, a photodiode having a light reception region that generates photocharges by light irradiation, a carrier pocket 6 in which the photocharges are accumulated, a P+ type high concentration diffusion layer 5 that discharges the photocharges accumulated in the carrier pocket, a modulation gate electrode that is formed over the carrier pocket through a gate dielectric film 1a, and a reset gate electrode 4a that is formed over a portion between the carrier pocket 6 and the P+ type high concentration diffusion layer 5 through a gate dielectric film 1b.

Abstract: A line sensor, includes a plurality of pixels which is arranged linearly, the number of the plurality of pixels including the number depending on a resolution, a first pixel group which is provided to a center portion of the plurality of pixels arranged linearly and has a pixel pitch shorter than a length corresponding to a pixel pitch calculated from the resolution, and a second pixel group which is provided to each of both side portions of the center portion, and has a pixel pitch longer than the length corresponding to the pixel pitch calculated from the resolution.

Abstract: A solid-state imaging device includes: a substrate; a photoelectric transducer that is provided within the substrate and generates light-generated charge in accordance with incident light; a floating diffusion that retains the light-generated charge generated from the photoelectric transducer; a transfer and retention unit that is provided between the photoelectric transducer and the floating diffusion for a purpose of controlling a transfer of the light-generated charge and has a charge-retaining region that can retain the light-generated charge generated from the photoelectric transducer; a reset unit that initializes a potential of the floating diffusion; an amplifying transistor that generates an output based on a potential of the floating diffusion; a selection transistor that selectively outputs an output of the amplifying transistor; and an excessive charge-discharging unit that discharges excessive electric charge generated from the photoelectric transducer.

Abstract: An apparatus including: a photodiode including: a first conductivity substrate; a second conductivity PD-well on the substrate's first surface side; and a first conductivity collection well inside the PD-well; a modulation transistor including: a second conductivity TR-well connected with the PD-well, and a junction depth shallower than that of the PD-well; a first conductivity modulation well inside the TR-well, and connected with the collection well; a second conductivity source inside the modulation well, and including a region contacting the first surface; a gate electrode in a region partially covering the modulation well and enclosing the source; a gate insulation layer between the gate and the first surface; and a second conductivity drain partially sandwiching the gate and opposing the source, and including a region contacting the first surface; and a transfer transistor connected to modulation transistors in pixels between the source and a connected source line.

Abstract: A solid state imaging device, including: a plurality of storage wells which stores an optically generated charge that is generated at a photoelectric conversion region corresponding to an incident light, the plurality of storage wells being inside a substrate; wherein a plurality of the photoelectric conversion regions is arrayed on the substrate in a two dimensional matrix; a plurality of amplifiers each installed per every pair of the photoelectric conversion regions that are adjacent in one direction of the two dimensional matrix, outputting a pixel signal that corresponds to the optically generated charge retained in a floating diffusion region; a plurality of transfer controlling elements, a pair of which is installed in every pair of the photoelectric conversion regions, changing a potential barrier of an optically generated charge transfer route, the transfer route being between each of the storage wells in the pair of the photoelectric conversion regions and the corresponding floating diffusion region

Abstract: A solid state imaging device comprises a substrate, a photoelectric conversion element, an accumulation well, a modulation well, a modulation transistor, a transfer control element, and an unwanted electric charge discharging control element. The photoelectric conversion element generates photo-generated electric charges corresponding to incident light, which are accumulated in the accumulation well. The transfer control element changes a potential barrier between the accumulation well and the modulation well. The modulation transistor has a channel threshold voltage controlled by the electric charges stored in the modulation well and outputs a pixel signal corresponding to the electric charges. The unwanted electric charge discharging control element discharges the electric charges that overflow from the accumulation well through the unwanted electric charge discharging channel.