Patents by Inventor Kazunobu Kuwazawa

Kazunobu Kuwazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050087672
    Abstract: A solid-state imaging device comprising: a photoelectric conversion element generating photo-generated charges; an accumulation well accumulating the charges; a modulation well holding the charges from the accumulation well; a modulation transistor controlled by the charges held in the modulation well and that outputs a signal corresponding to the charges; a transfer control element changing the potential barrier of a transfer channel between the accumulation and modulation wells to control transfer of the charges; an unwanted charges discharging control element controlling the potential barrier of an unwanted charges discharging channel coupled to the accumulation well, and discharging charges that overflow from the accumulation well during a period other than the transfer period when the photo-generated charges are transferred; and a residual charges discharging control element controlling the potential barrier of a residual charges discharging channel coupled to the modulation well, and discharging residua
    Type: Application
    Filed: September 8, 2004
    Publication date: April 28, 2005
    Inventors: Kazunobu Kuwazawa, Yutaka Maruo, Sanae Nishida, Yoshitaka Narita
  • Publication number: 20050087781
    Abstract: An imaging device comprising: a photoelectric conversion element generating photo-generated charges; an accumulation well accumulating the charges; a modulation well storing the charges; a modulation transistor having a channel threshold voltage controlled by the stored charges and outputting a corresponding signal; a transfer control element having a control end coupled to a control end of the modulation transistor and controlling the potential barrier of a transfer channel between the accumulation and modulation wells, and controlling transfer of the charges; an unwanted electric charge discharging control element controlling the potential barrier of an unwanted electric charge discharging channel coupled to the accumulation well, and discharging charges overflowing from the accumulation well during a period except for the charges transfer period; and a residual charge discharging control element controlling the potential barrier of a residual electric charge discharging channel coupled to the modulation we
    Type: Application
    Filed: September 8, 2004
    Publication date: April 28, 2005
    Inventors: Kazunobu Kuwazawa, Yutaka Maruo, Sanae Nishida, Yoshitaka Narita
  • Publication number: 20050087773
    Abstract: A solid state imaging device including: a photoelectric conversion element generating photo-generated charges corresponding to incident light; an accumulation well accumulating photo-generated charges; a modulation well storing photo-generated charges from the accumulation well; a modulation transistor whose channel threshold voltage is controlled by the stored photo-generated charges and that outputs a pixel signal corresponding to the photo-generated charges; a transfer control element changing the potential barrier of a transfer channel between the accumulation well and the modulation well to control transfer of the photo-generated charges; and an unwanted charges discharge control element controlling the potential barrier of an unwanted charges discharge channel coupled to the accumulation well, and discharging charges which overflow from the accumulation well through the unwanted charges discharge channel during all periods other than the transfer period when photo-generated charges are transferred from
    Type: Application
    Filed: September 8, 2004
    Publication date: April 28, 2005
    Inventor: Kazunobu Kuwazawa
  • Publication number: 20050088553
    Abstract: A solid state imaging device including: a photoelectric conversion element generating photo-generated electric charges corresponding to incident light; an accumulation well accumulating photo-generated electric charges; a modulation well storing photo-generated electric charges from the accumulation well; a modulation transistor whose channel threshold voltage is controlled by the stored photo-generated electric charges and that outputs a pixel signal corresponding to photo-generated electric charges; a transfer control element changing the potential barrier of a transfer channel between the accumulation well and the modulation well, and controlling transfer of photo-generated electric charges; and an unwanted electric charge discharging control element controlling the potential barrier of an unwanted electric charge discharging channel coupled to the accumulation well, and discharging the electric charges overflowing from the accumulation well through the unwanted electric charge discharging channel for all
    Type: Application
    Filed: September 8, 2004
    Publication date: April 28, 2005
    Inventor: Kazunobu Kuwazawa
  • Publication number: 20050082589
    Abstract: A first conductive layer, a dielectric layer and a second conductive layer are continuously deposited, the second conductive layer is patterned and the upper electrode 13a of the MIM capacitor C is formed, and subsequently, a protective layer is deposited on the entire face. Next, the protective layer is patterned, and at the same time, the dielectric layer is also patterned with the same mask and the capacitive insulation layer 12a of the MIM capacitor is formed. Next, using the protective layer as a hard mask, the first conductive layer is patterned, and the lower electrode 11a and the wiring 11b of the MIM capacitor are formed. Because the MIM capacitor C is formed as the above, the outer circumferential shape of the lower electrode 11a is generally the same as that of the capacitive insulation layer 12a.
    Type: Application
    Filed: September 2, 2004
    Publication date: April 21, 2005
    Inventors: Takafumi Noda, Yoshinobu Yusa, Kazunobu Kuwazawa
  • Patent number: 6730947
    Abstract: The present invention is characterized in comprising a semiconductor substrate, an embedded impurity layer of a first conductive type provided in the semiconductor substrate, a first impurity region of the first conductive type that becomes a first well region provided in the semiconductor substrate above the embedded impurity layer, a second impurity region of a second conductive type, which is an opposite conductive type to the first conductive type, that becomes a second well region provided in the semiconductor substrate in proximity to the first impurity region above the embedded impurity layer, and a third impurity region of the second conductive type that is provided around a region including the first impurity region and the second impurity region in the semiconductor substrate, and that becomes a guard ring region that electrically connects to the second impurity region.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: May 4, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Kazunobu Kuwazawa
  • Patent number: 6608348
    Abstract: A semiconductor device comprises a memory cell array in which a plurality of nonvolatile semiconductor memory devices are arrayed in a row direction and a column direction. Each of the nonvolatile semiconductor memory devices includes a silicon semiconductor substrate, a floating gate disposed on the silicon semiconductor substrate through a gate insulating layer interposed therebetween, a second insulating layer disposed on the floating gate, and a control gate which is isolated from the floating gate and extends in the row direction. The nonvolatile semiconductor memory devices which are adjacent each other in the row direction are isolated by element isolation regions extending in the column direction. One of angles formed where a major axis direction of the floating gate in a planar configuration of the memory cell array intersects the column direction is an acute angle.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: August 19, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Kazunobu Kuwazawa
  • Publication number: 20030119265
    Abstract: A semiconductor memory device may be formed from a pair of transfer MOS transistors 1, 2 controlled by a word line 11 and a pair of data retaining flip-flop circuit formed from serially connected load elements 5, 6 and drive MOS transistors 3, 4. In the semiconductor memory device, the transfer MOS transistors 1, 2 have a threshold voltage greater than a threshold voltage of the drive MOS transistors 3, 4. The memory device may display an improved &bgr; ratio, and reduce the size of the drive MOS transistors to thereby reduce the cell area.
    Type: Application
    Filed: February 3, 2003
    Publication date: June 26, 2003
    Inventor: Kazunobu Kuwazawa
  • Patent number: 6579764
    Abstract: An integrated circuit device is provided that has a split-gate type memory transistor, a first capacitor element and a second capacitor element formed on a common chip. The dielectric strength of each of the split-gate type memory transistor, the first capacitor element and the second capacitor element can be improved. An intermediate insulation film of the split-gate type memory transistor can include a thermal oxide film, an HTO film, a side-section insulation film, and another thermal oxide film. A dielectric film of the first capacitor element can include a thermal oxide film, an HTO film, and another thermal oxide film, while a dielectric film of the second capacitor element can include a thermal oxide film, an HTO film, a silicon nitride film, and another thermal oxide film.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: June 17, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Kazunobu Kuwazawa
  • Patent number: 6528897
    Abstract: A semiconductor memory device may be formed from a pair of transfer MOS transistors 1, 2 controlled by a word line 11 and a pair of data retaining flip-flop circuit formed from serially connected load elements 5, 6 and drive MOS transistors 3, 4. In the semiconductor memory device, the transfer MOS transistors 1, 2 have a threshold voltage greater than a threshold voltage of the drive MOS transistors 3, 4. The memory device may display an improved &bgr; ratio, and reduce the size of the drive MOS transistors to thereby reduce the cell area.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: March 4, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Kazunobu Kuwazawa
  • Publication number: 20030034493
    Abstract: The present invention is characterized in comprising a semiconductor substrate, an embedded impurity layer of a first conductive type provided in the semiconductor substrate, a first impurity region of the first conductive type that becomes a first well region provided in the semiconductor substrate above the embedded impurity layer, a second impurity region of a second conductive type, which is an opposite conductive type to the first conductive type, that becomes a second well region provided in the semiconductor substrate in proximity to the first impurity region above the embedded impurity layer, and a third impurity region of the second conductive type that is provided around a region including the first impurity region and the second impurity region in the semiconductor substrate, and that becomes a guard ring region that electrically connects to the second impurity region.
    Type: Application
    Filed: July 18, 2002
    Publication date: February 20, 2003
    Inventor: Kazunobu Kuwazawa
  • Publication number: 20030030114
    Abstract: A gate electrode 14 is formed through a gate oxide film 13 over a channel region 12 in an element region 11, and sidewall dielectric films 16 are provided on side sections of the gate electrode 14. Source/drain regions 17 include low concentration impurity regions 171 and high concentration impurity regions 172. The impurity regions 172 are provided, by an over-etching method when forming the sidewalls 16, at a disposition level LV2 in the element region 11, which is lower than a disposition level LV1 where the impurity regions 171 are disposed. Assisting impurity regions 173 are provided in regions where the levels change between level LV1 and LV2. As a result, the continuity of impurity regions between the impurity regions 172 and the impurity regions 171 that are low concentration extension regions is secured, the their electrical connection is stabilized.
    Type: Application
    Filed: July 12, 2002
    Publication date: February 13, 2003
    Inventor: Kazunobu Kuwazawa
  • Publication number: 20020197788
    Abstract: An integrated circuit device is provided that has a split-gate type memory transistor, a first capacitor element and a second capacitor element formed on a common chip. The dielectric strength of each of the split-gate type memory transistor, the first capacitor element and the second capacitor element can be improved. An intermediate insulation film of the split-gate type memory transistor can include a thermal oxide film, an HTO film, a side-section insulation film, and another thermal oxide film. A dielectric film of the first capacitor element can include a thermal oxide film, an HTO film, and another thermal oxide film, while a dielectric film of the second capacitor element can include a thermal oxide film, an HTO film, a silicon nitride film, and another thermal oxide film.
    Type: Application
    Filed: August 15, 2002
    Publication date: December 26, 2002
    Applicant: SEIKO EPSON CORPORATION.
    Inventor: Kazunobu Kuwazawa
  • Publication number: 20020190314
    Abstract: Embodiments include methods for manufacturing semiconductor devices and semiconductor devices in which an extension region, a source region and a drain region can be simultaneously formed. One method for manufacturing a semiconductor device includes (a) forming a gate dielectric layer 20 over a semiconductor substrate 10; (b) forming a gate electrode 22 over the gate dielectric layer 20; (c) forming an extension control layer 40 over the semiconductor substrate 10 on sides of the gate dielectric layer 20; and (d) forming a source region 24 and a drain region 26 by ion-implanting an impurity 80 in the semiconductor substrate 10, wherein an extension region 30 is formed in the semiconductor substrate 10 below the extension control layer 40 with the source region 24 and the drain region 26.
    Type: Application
    Filed: June 19, 2001
    Publication date: December 19, 2002
    Inventor: Kazunobu Kuwazawa
  • Patent number: 6476436
    Abstract: A semiconductor device has a first capacitor component and a second capacitor component on a silicon substrate. In the semiconductor device, the first capacitor component has a first lower electrode composed of an impurity-doped polycrystal silicon film, a first insulation film formed on the first lower electrode, and a first upper electrode formed on the first insulation film. The second capacitor component has a second lower electrode formed from an impurity-doped polycrystal silicon film having an impurity concentration different from an impurity concentration of the polycrystal silicon film of the first lower electrode, a second insulation film formed on the second lower electrode and a second upper electrode formed on a second insulation film.
    Type: Grant
    Filed: January 19, 2000
    Date of Patent: November 5, 2002
    Assignee: Seiko Epson Corporation
    Inventor: Kazunobu Kuwazawa
  • Patent number: 6462370
    Abstract: An integrated circuit device is provided that has a split-gate type memory transistor, a first capacitor element and a second capacitor element formed on a common chip. The dielectric strength of each of the split-gate type memory transistor, the first capacitor element and the second capacitor element can be improved. An intermediate insulation film of the split-gate type memory transistor can include a thermal oxide film, an HTO film, a side-section insulation film, and another thermal oxide film. A dielectric film of the first capacitor element can include a thermal oxide film, an HTO film, and another thermal oxide film, while a dielectric film of the second capacitor element can include a thermal oxide film, an HTO film, a silicon nitride film, and another thermal oxide film.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: October 8, 2002
    Assignee: Seiko Epson Corporation
    Inventor: Kazunobu Kuwazawa
  • Publication number: 20020079515
    Abstract: A semiconductor memory device may be formed from a pair of transfer MOS transistors 1, 2 controlled by a word line 11 and a pair of data retaining flip-flop circuit formed from serially connected load elements 5, 6 and drive MOS transistors 3, 4. In the semiconductor memory device, the transfer MOS transistors 1, 2 have a threshold voltage greater than a threshold voltage of the drive MOS transistors 3, 4. The memory device may display an improved &bgr; ratio, and reduce the size of the drive MOS transistors to thereby reduce the cell area.
    Type: Application
    Filed: November 29, 2001
    Publication date: June 27, 2002
    Inventor: Kazunobu Kuwazawa
  • Publication number: 20020068428
    Abstract: A semiconductor device comprises a SOI substrate formed of a semiconductor substrate, an insulation layer provided above the semiconductor substrate, and a SOI layer provided above the insulation layer. An impurity layer is provided in the semiconductor substrate. The impurity layer is electrically connected to a wiring layer provided above the SOI layer. The impurity layer can function as either a wiring layer or a resistance layer. This semiconductor device makes it possible to utilize the region above the semiconductor layer efficiently.
    Type: Application
    Filed: August 29, 2001
    Publication date: June 6, 2002
    Inventor: Kazunobu Kuwazawa
  • Publication number: 20020048200
    Abstract: An integrated circuit device is provided that has a split-gate type memory transistor, a first capacitor element and a second capacitor element formed on a common chip. The dielectric strength of each of the split-gate type memory transistor, the first capacitor element and the second capacitor element can be improved. An intermediate insulation film of the split-gate type memory transistor can include a thermal oxide film, an HTO film, a side-section insulation film, and another thermal oxide film. A dielectric film of the first capacitor element can include a thermal oxide film, an HTO film, and another thermal oxide film, while a dielectric film of the second capacitor element can include a thermal oxide film, an HTO film, a silicon nitride film, and another thermal oxide film.
    Type: Application
    Filed: August 31, 2001
    Publication date: April 25, 2002
    Inventor: Kazunobu Kuwazawa
  • Publication number: 20020017679
    Abstract: A semiconductor device comprises a memory cell array in which a plurality of nonvolatile semiconductor memory devices are arrayed in a row direction and a column direction. Each of the nonvolatile semiconductor memory devices includes a silicon semiconductor substrate, a floating gate disposed on the silicon semiconductor substrate through a gate insulating layer interposed therebetween, a second insulating layer disposed on the floating gate, and a control gate which is isolated from the floating gate and extends in the row direction. The nonvolatile semiconductor memory devices which are adjacent each other in the row direction are isolated by element isolation regions extending in the column direction. One of angles formed where a major axis direction of the floating gate in a planar configuration of the memory cell array intersects the column direction is an acute angle.
    Type: Application
    Filed: March 7, 2001
    Publication date: February 14, 2002
    Inventor: Kazunobu Kuwazawa