Patents by Inventor Kazuo Tanaka

Kazuo Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8646438
    Abstract: An air intake duct (54) for fluid connecting between an air intake control valve unit (52) and a supercharger (60) includes a duct inlet (56) fluid connected with an outlet port (52b) of the air intake control valve (52) and oriented in a first direction (D1), a duct outlet (58) fluid connected with a suction port (60a) of the supercharger (60) and oriented in a second direction (D2) substantially perpendicular to the first direction (D1), and a duct body (74) for defining an air intake passage (78) extending from the duct inlet (56) to the duct outlet (58). The duct body (74) has a portion confronting the duct outlet (58), which is formed with a guide projection (80) that protrudes towards the duct outlet (58).
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: February 11, 2014
    Assignee: Kawasaki Jukogyo Kabushiki Kaisha
    Inventors: Daisuke Saeki, Kazuo Tanaka
  • Publication number: 20130341728
    Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
    Type: Application
    Filed: August 27, 2013
    Publication date: December 26, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Takahiro HAYASHI, Shunsuke TOYOSHIMA, Kazuo SAKAMOTO, Naozumi MORINO, Kazuo TANAKA
  • Patent number: 8590141
    Abstract: The object of the invention is to provide a method and an apparatus that allow production of metal plate chip resistors having a relatively low resistance with high accuracy and yield through simple process. The object is achieved by apparatus 10 for manufacturing metal plate chip resistors including cutting mold 21 for cutting intermediate product strip 14 transversely to obtain worked product chip 16a, ohm meter 22 for measuring the resistance of the worked product chip 16a, control device 23 having a calculating part for performing a calculation using the resistance measured by the ohm meter 22 to work out a width in which the strip 14 is to be cut transversely so as to obtain a worked product chip of a desired resistance, and cutting width adjusting means 26, 27 for making an adjustment so that the strip 14 is to be cut transversely in the width obtained from the calculating part.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: November 26, 2013
    Assignee: Kamaya Electric Co., Ltd.
    Inventors: Tatsuki Hirano, Kazuo Tanaka
  • Patent number: 8584783
    Abstract: A motorcycle includes a combustion engine (E) of a type, in which a cylinder block (34) protrudes upwardly from a crankcase (32), an air cleaner unit (42) for substantially purifying an air, and a supercharger (44) for taking a substantially purified air from the air cleaner unit (42) thereinto and supplying the air towards the combustion engine (E). The supercharger (44) is disposed rearwardly of the cylinder block (34) and the air cleaner unit (42) is disposed rearwardly thereof. Also, a surge tank (48) is disposed rearwardly upwardly of the cylinder block (34) of the combustion engine (E) and above the supercharger (44).
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: November 19, 2013
    Assignee: Kawasaki Jukogyo Kabushiki Kaisha
    Inventors: Daisuke Saeki, Kazuo Tanaka
  • Publication number: 20130264647
    Abstract: A semiconductor integrated circuit device with a “PAD on I/O cell” structure in which a pad lead part is disposed almost in the center of an I/O part so as to reduce the chip layout area. In the I/O part, a transistor lies nearest to the periphery of the semiconductor chip. When seen in a plan view of the I/O part, a resistance lies above the transistor and a first and a second diode lie above the resistance; a second transistor lies above the diodes; and a logic block lies above the second transistor with a pad lead part, for example, formed in a metal wiring layer, therebetween. This permits the pad through the second transistor to be on the same node and therefore the pad lead part can be disposed almost in the center of the I/O part.
    Type: Application
    Filed: June 5, 2013
    Publication date: October 10, 2013
    Inventors: Takeo TOBA, Kazuo TANAKA, Hiroyasu ISHIZUKA
  • Patent number: 8552561
    Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: October 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
  • Publication number: 20130205726
    Abstract: [Problem to be Solved] To enhance the performance for separation of oil mist from blow-by gas. [Solution] A filter element 13 which is to be attached to an oil separator unit 3 includes a core 31. This core is a double tube having an internal cylindrical member 34 and an external cylindrical member 35, and a space between the internal cylindrical member and the external cylindrical member is used as a separation chamber 36. An injection hole 39 for injecting blow-by gas while increasing its flow velocity is provided in the internal cylindrical member. A surface which is an inner wall surface of the external cylindrical member and which faces the injection hole is a spraying surface onto which the blow-by gas injected from the injection hole is sprayed. Moreover, an opening for oil discharge from which oil OL condensed on the spraying surface is discharged, and an opening for discharge from which the blow-by gas from which oil mist has been separated is discharged are provided in the core.
    Type: Application
    Filed: June 24, 2010
    Publication date: August 15, 2013
    Applicant: TOKYO ROKI CO. LTD.
    Inventors: Masaya Wada, Kosaku Ishida, Kazuki Shirakura, Yuta Endo, Yoshitaka Nakamura, Kazuo Tanaka, Takatsugu Kurosawa, Jun Takashima
  • Publication number: 20130049864
    Abstract: An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.
    Type: Application
    Filed: August 20, 2012
    Publication date: February 28, 2013
    Inventors: Natsuki IKEHATA, Kazuo Tanaka, Takeo Toba, Masashi Arakawa
  • Patent number: 8299628
    Abstract: There is provided a method of mounting conductive balls on pads on a substrate. The method includes: (a) placing the substrate having the pads coated with an adhesive over a container for containing the conductive balls therein and whose top surface is open such that the pads faces the top surface of the container; and (b) throwing up the conductive balls in the container by moving the container up and down at a given stroke, thereby allowing the conductive balls to adhere to the adhesive coated on the pads. Step (b) is repeatedly performed.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: October 30, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Hideaki Sakaguchi, Kiyoaki Iida, Kazuo Tanaka
  • Patent number: 8299283
    Abstract: The present invention provides a contrast agent which ensures 1) high contrast performance, 2) low toxicity, and 3) a simple production process. The present invention provides a contrast agent containing a silsesquioxane represented by General Formula (I), wherein R1, the same or different, is a substituent bonded to Si through a carbon atom, the substituent having, at its terminal, a group represented by General Formula (II), wherein p represents an integer of from 1 to 5; q is the same or different, and represents an integer of from 1 to 5; R2 is the same or different, and represents hydrogen atom, alkyl group, aralkyl group or acyl group, or a group represented by General Formula (III), wherein p, q and R2 are the same as above.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: October 30, 2012
    Assignee: Kyoto University
    Inventors: Yoshiki Chujo, Kazuo Tanaka, Kensuke Naka
  • Publication number: 20120267182
    Abstract: A motorcycle includes a combustion engine (E) of a type, in which a cylinder block (34) protrudes upwardly from a crankcase (32), an air cleaner unit (42) for substantially purifying an air, and a supercharger (44) for taking a substantially purified air from the air cleaner unit (42) thereinto and supplying the air towards the combustion engine (E). The supercharger (44) is disposed rearwardly of the cylinder block (34) and the air cleaner unit (42) is disposed rearwardly thereof. Also, a surge tank (48) is disposed rearwardly upwardly of the cylinder block (34) of the combustion engine (E) and above the supercharger (44).
    Type: Application
    Filed: June 22, 2012
    Publication date: October 25, 2012
    Inventors: Daisuke SAEKI, Kazuo TANAKA
  • Publication number: 20120268167
    Abstract: A pull-up circuit prevents generation of a leak current if a difference of potentials occurs between a power source voltage of a pull-up circuit (a bus-hold circuit) and an input terminal. A control terminal is provided in the bus-hold circuit. Inputs of the input terminal and the control terminal are input to a NOR gate, and an output of the NOR gate is input to a gate terminal of a first MOSFET that controls coupling between an input terminal and the power source voltage of the bus-hold circuit. A second MOSFET (“control” MOSFET) is provided as a switch that operates by an inverted output of the control terminal. By coupling the first MOSFET and the control MOSFET in series, the coupling between the input terminal and the power source voltage is controlled with a higher precision, thereby preventing generation of a leak current.
    Type: Application
    Filed: July 2, 2012
    Publication date: October 25, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Toshio Yamada, Kazuo Tanaka, Akinobu Watanabe, Shigeru Yamamoto, Yukio Hiraiwa
  • Publication number: 20120260896
    Abstract: An air intake duct (54) for fluid connecting between an air intake control valve unit (52) and a supercharger (60) includes a duct inlet (56) fluid connected with an outlet port (52b) of the air intake control valve (52) and oriented in a first direction (D1), a duct outlet (58) fluid connected with a suction port (60a) of the supercharger (60) and oriented in a second direction (D2) substantially perpendicular to the first direction (D1), and a duct body (74) for defining an air intake passage (78) extending from the duct inlet (56) to the duct outlet (58). The duct body (74) has a portion confronting the duct outlet (58), which is formed with a guide projection (80) that protrudes towards the duct outlet (58).
    Type: Application
    Filed: June 25, 2012
    Publication date: October 18, 2012
    Inventors: Daisuke SAEKI, Kazuo TANAKA
  • Patent number: 8288325
    Abstract: The present invention provides a lubricant composition for hot forming which makes it possible to provide lubricity at 80° C. or more without being peeled or washed by the roll cooling water, and which is easily washed under 40° C. without having water resistance. The lubricant composition for hot forming of the present invention comprises: a solid lubricant from 10 to 40% by mass; water-dispersible synthetic resin from 5 to 20% by mass; inorganic acid amine salt from 0.5 to 5% by mass; and water from 45 to 80% by mass.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: October 16, 2012
    Assignee: Sumitomo Metal Industries, Ltd.
    Inventors: Kenichi Sasaki, Sumio Iida, Shizuo Mori, Kazuo Tanaka
  • Publication number: 20120233398
    Abstract: The present invention comprises a CHA 110 which transmits/receives data to/from an external device, a DKA 140 which transmits/receives data to/from an HDD unit 200, a primary cache unit 120 which has a primary cache memory 124, a secondary cache unit 130 which is installed between the primary cache unit 120 and the DKA 140 and has a secondary cache memory 134, a CCP 121 which stores write target data received by the CHA 110 in the primary cache memory 124, and a CCP 131 which stores the write target data in the secondary cache memory 134, and transfers the write target data stored in the secondary cache memory 134 to the DKA 140.
    Type: Application
    Filed: May 24, 2012
    Publication date: September 13, 2012
    Applicant: HITACHI, LTD.
    Inventors: Tatsuya NINOMIYA, Kazuo TANAKA
  • Patent number: 8237469
    Abstract: A pull-up circuit prevents generation of a leak current if a difference of potentials occurs between a power source voltage of a pull-up circuit (a bus-hold circuit) and an input terminal. A control terminal is provided in the bus-hold circuit. Inputs of the input terminal and the control terminal are input to a NOR gate, and an output of the NOR gate is input to a gate terminal of a first MOSFET that controls coupling between an input terminal and the power source voltage of the bus-hold circuit. A second MOSFET (“control” MOSFET) is provided as a switch that operates by an inverted output of the control terminal. By coupling the first MOSFET and the control MOSFET in series, the coupling between the input terminal and the power source voltage is controlled with a higher precision, thereby preventing generation of a leak current.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: August 7, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshio Yamada, Kazuo Tanaka, Akinobu Watanabe, Shigeru Yamamoto, Yukio Hiraiwa
  • Publication number: 20120154965
    Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.
    Type: Application
    Filed: February 28, 2012
    Publication date: June 21, 2012
    Applicants: HITACHI ULSI SYSTEMS CO., LTD., RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuo Tanaka, Hiroyuki Mizuno, Rie Nishiyama, Manabu Miyamoto
  • Patent number: 8200897
    Abstract: The present invention comprises a CHA 110 which transmits/receives data to/from an external device, a DKA 140 which transmits/receives data to/from an HDD unit 200, a primary cache unit 120 which has a primary cache memory 124, a secondary cache unit 130 which is installed between the primary cache unit 120 and the DKA 140 and has a secondary cache memory 134, a CCP 121 which stores write target data received by the CHA 110 in the primary cache memory 124, and a CCP 131 which stores the write target data in the secondary cache memory 134, and transfers the write target data stored in the secondary cache memory 134 to the DKA 140.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: June 12, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Tatsuya Ninomiya, Kazuo Tanaka
  • Patent number: 8173806
    Abstract: In reacting an anthranilic acid derivative represented by the general formula (1), especially the anthranilic acid derivative selected from anthranilic acid, anthranilamide and anthranilate, with formamide, the reaction is attained under the condition of coexistence of acetic acid and a base as a catalyst in the reaction liquid, and it has made it possible to produce a quinazolin-4-one derivative represented by the general formula (2) and useful as a material for medicine intermediates, at high yield with no side production.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: May 8, 2012
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Kazuo Tanaka, Yoshifumi Sato, Takafumi Yoshimura
  • Publication number: 20120094010
    Abstract: Provided is a substrate processing apparatus capable of suppressing inferiority when heat treatment is controlled using a temperature sensor.
    Type: Application
    Filed: July 28, 2011
    Publication date: April 19, 2012
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Shinobu SUGIURA, Masaaki UENO, Kazuo TANAKA, Masashi SUGISHITA, Hideto YAMAGUCHI, Kenji SHIRAKO