Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.

Abstract: To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD.

Abstract: The object of the invention is to provide a method and an apparatus that allow production of metal plate chip resistors having a relatively low resistance with high accuracy and yield through simple process. The object is achieved by apparatus 10 for manufacturing metal plate chip resistors including cutting mold 21 for cutting intermediate product strip 14 transversely to obtain worked product chip 16a, ohm meter 22 for measuring the resistance of the worked product chip 16a, control device 23 having a calculating part for performing a calculation using the resistance measured by the ohm meter 22 to work out a width in which the strip 14 is to be cut transversely so as to obtain a worked product chip of a desired resistance, and cutting width adjusting means 26, 27 for making an adjustment so that the strip 14 is to be cut transversely in the width obtained from the calculating part.

Abstract: The present invention comprises a CHA 110 which transmits/receives data to/from an external device, a DKA 140 which transmits/receives data to/from an HDD unit 200, a primary cache unit 120 which has a primary cache memory 124, a secondary cache unit 130 which is installed between the primary cache unit 120 and the DKA 140 and has a secondary cache memory 134, a CCP 121 which stores write target data received by the CHA 110 in the primary cache memory 124, and a CCP 131 which stores the write target data in the secondary cache memory 134, and transfers the write target data stored in the secondary cache memory 134 to the DKA 140.

Abstract: A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.

Abstract: The present invention comprises a CHA 110 which transmits/receives data to/from an external device, a DKA 140 which transmits/receives data to/from an HDD unit 200, a primary cache unit 120 which has a primary cache memory 124, a secondary cache unit 130 which is installed between the primary cache unit 120 and the DKA 140 and has a secondary cache memory 134, a CCP 121 which stores write target data received by the CHA 110 in the primary cache memory 124, and a CCP 131 which stores the write target data in the secondary cache memory 134, and transfers the write target data stored in the secondary cache memory 134 to the DKA 140.

Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.

Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.

Abstract: A protection circuit with suppressed erroneous operation due to power source fluctuation has a first resistor and a capacitor connected in series between a power source line and a ground line, an inverter with an input connected between the first resistor and the capacitor, and a MOS transistor with a gate electrode that receives an output of the inverter and with a drain electrode and source electrode connected to the power source line and the ground line. When high voltage fluctuation occurs in the power source line, a level change at a connection point between the first resistor and the capacitor is delayed according to a time constant. By the delay, the MOS transistor that receives an output of the inverter is temporarily turned on and discharges a high voltage to the ground line.

Abstract: To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD.

Abstract: A pull-up circuit prevents generation of a leak current if a difference of potentials occurs between a power source voltage of a pull-up circuit (a bus-hold circuit) and an input terminal. A control terminal is provided in the bus-hold circuit. Inputs of the input terminal and the control terminal are input to a NOR gate, and an output of the NOR gate is input to a gate terminal of a first MOSFET that controls coupling between an input terminal and the power source voltage of the bus-hold circuit. A second MOSFET (“control” MOSFET) is provided as a switch that operates by an inverted output of the control terminal. By coupling the first MOSFET and the control MOSFET in series, the coupling between the input terminal and the power source voltage is controlled with a higher precision, thereby preventing generation of a leak current.

Abstract: A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.

Abstract: In a conductive ball mounting apparatus for mounting one conductive ball on each of a plurality of pads which are provided on a substrate and on which an adhesive is formed, the conductive ball mounting apparatus includes: a conductive ball container for containing a plurality of conductive balls therein and having an opening to pass through the plurality of conductive balls; a substrate holder disposed over the conductive ball container to face the opening, and holding the substrate in such a manner that the plurality of conductive balls and the plurality of pads face each other and the substrate is disposed over the conductive ball container with a space therebetween; and a conductive ball supplying unit for supplying the plurality of conductive balls to the plurality of pads via the opening by moving up the plurality of conductive balls.

Abstract: There is provided a method of mounting conductive balls on pads on a substrate. The method includes: (a) placing the substrate having the pads coated with an adhesive over a container for containing the conductive balls therein and whose top surface is open such that the pads faces the top surface of the container; and (b) throwing up the conductive balls in the container by moving the container up and down at a given stroke, thereby allowing the conductive balls to adhere to the adhesive coated on the pads. Step (b) is repeatedly performed.

Abstract: The present invention provides a lubricant composition for hot forming which makes it possible to provide lubricity at 80° C. or more without being peeled or washed by the roll cooling water, and which is easily washed under 40° C. without having water resistance. The lubricant composition for hot forming of the present invention comprises: a solid lubricant from 10 to 40% by mass; water-dispersible synthetic resin from 5 to 20% by mass; inorganic acid amine salt from 0.5 to 5% by mass; and water from 45 to 80% by mass.

Abstract: In a method of removing conductive balls that are left on a mask provided on a substrate having pads thereon, the method includes: (a) making a sheet member close to the mask using a contacting mechanism such that a gap between the sheet member and the mask is set small than a diameter of the conductive balls. The conductive balls are removed in such a manner that the conductive balls are adhered onto the sheet member.

Abstract: To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD.

Abstract: A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.

Abstract: A method of mounting conductive balls on pads on a substrate includes: (a) placing the substrate having the pads coated with an adhesive over a container for containing the conductive balls therein and whose top surface is open such that the pads faces the top surface of the container; and (b) throwing up the conductive balls in the container by moving the container up and down at a given stroke, thereby allowing the conductive balls to adhere to the adhesive coated on the pads. Step (b) is repeatedly performed.

Abstract: The present invention provides a lubricant composition for hot forming which makes it possible to provide lubricity at 80° C. or more without being peeled or washed by the roll cooling water, and which is easily washed under 40° C. without having water resistance. The lubricant composition for hot forming of the present invention comprises: a solid lubricant from 10 to 40% by mass; water-dispersible synthetic resin from 5 to 20% by mass; inorganic acid amine salt from 0.5 to 5% by mass; and water from 45 to 80% by mass.