Patents by Inventor Kazuo Tanaka

Kazuo Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070120258
    Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
    Type: Application
    Filed: November 28, 2006
    Publication date: May 31, 2007
    Inventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
  • Patent number: 7214343
    Abstract: The method for producing a granulated powder of the present invention includes the steps of: preparing an R—Fe—B alloy powder; and granulating the alloy powder using at least one kind of granulating agent selected from normal paraffins, isoparaffins and depolymerized oligomers, to prepare a granulated powder. The produced R—Fe—B alloy granulated powder is excellent in flowability and compactibility as well as in binder removability.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: May 8, 2007
    Assignee: Neomax Co., Ltd.
    Inventors: Futoshi Kuniyoshi, Yuji Kaneko, Akihito Tsujimoto, Kazunari Shimauchi, Kazuo Tanaka, Shizuo Mori, Kiyofumi Suzuki
  • Patent number: 7204077
    Abstract: Techniques suitable for recovering energy from a high-temperature gas of an ordinary pressure are provided. A turbomachine has a turbine 16 and compressors 20 and 24. A combustor 12 is disposed at a stage above the turbine 16. A power generating system generates power by passing a working fluid for the turbomachine through the combustor 12, the turbine 16 and the compressors 20 and 24 in that order.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: April 17, 2007
    Assignees: Kawasaki Jukogyo Kabushiki Kaisha, National Institute of Advanced Industrial Science & Technology
    Inventors: Kazuo Tanaka, Seiji Yamashita, Eiichi Harada, Norihiko Iki, Sanyo Takahashi, Hirohide Furutani
  • Patent number: 7205396
    Abstract: A nucleic acid base for hole transportation in DNAs which does not cause oxidative decomposition; and an artificial DNA molecule which can realize effective hole transportation in DNAs while maintaining the double spiral structure of the DNAs. Provided are: a nucleic acid which contains a benzodeazaadenine derivative base represented by the general formula (I): (wherein R1, R2, R3, R4, R5, and R6 each independently represents hydrogen, amino, mono (lower alkyl) amino, di (lower alkyl) amino, hydroxy, lower alkoxy, halogeno, cyano, mercapto, lower alkylthio, or aryl; and R7 and R8 each independently represents hydrogen or a group bonded to phosphoric acid); and a polynucleotide comprising the nucleic acid.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: April 17, 2007
    Assignee: Japan Science and Technology Agency
    Inventors: Isao Saito, Akimitsu Okamoto, Kazuo Tanaka
  • Publication number: 20070019493
    Abstract: The present invention provides a semiconductor integrated circuit having two kinds of input/output circuits realizing higher speed and higher packing density with rational configuration. The semiconductor integrated circuit has a first input/output circuit operating on a first power source voltage, an internal circuit operating on a second power source voltage lower than the first power source voltage, and a second input/output circuit operating on a third power source voltage lower than the first power source voltage. In an output circuit of the first input/output circuit, signal amplitude corresponding to the second power source voltage is converted to signal amplitude corresponding to the first power source voltage by a level shifter, and a P-channel MOSFET and an N-channel MOSFET constructing the output circuit are driven.
    Type: Application
    Filed: June 14, 2006
    Publication date: January 25, 2007
    Inventors: Takeo Toba, Kazuo Tanaka, Shunsuke Toyoshima
  • Publication number: 20060273825
    Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.
    Type: Application
    Filed: July 12, 2006
    Publication date: December 7, 2006
    Inventors: Kazuo Tanaka, Hiroyuki Mizuno, Rie Nishiyama, Manabu Miyamoto
  • Publication number: 20060232307
    Abstract: A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.
    Type: Application
    Filed: April 18, 2006
    Publication date: October 19, 2006
    Inventors: Yusuke Kanno, Kazuo Tanaka, Shunsuke Toyoshima, Takeo Toba
  • Publication number: 20060222919
    Abstract: A fuel cell-atmospheric-pressure turbine hybrid system uses the thermal energy of a cell exhaust gas discharged from an atmospheric-pressure, high-temperature fuel cell effectively, does not need any additional emergency protective device, and enables the use of lightweight, easy-to-process structural and piping materials to reduces the cost. The fuel cell-atmospheric-pressure turbine hybrid system includes: a combustor 2 for burning an exhaust gas G1 discharged from an atmospheric-pressure, high-temperature fuel cell 1; a turbine 3 in which a combustion gas G2 discharged from the combustor 2 expands and the pressure of the combustion gas G2 drops to a negative pressure; a compressor 4 for compressing an exhaust gas G3 discharged from the turbine 3 to increase the pressure of the exhaust gas G3; and a heat exchanger 5 for transferring heat from the high-temperature exhaust gas G3 discharged from the turbine 3 to low-temperature air A to be supplied to the fuel cell 1.
    Type: Application
    Filed: June 29, 2004
    Publication date: October 5, 2006
    Applicant: Kawasaki Jukogyo Kabushiki Kaisha
    Inventors: Kazuo Tanaka, Eiichi Harada, Takatoshi Shoji, Junichi Kitajima, Seiji Yamashita
  • Publication number: 20060188240
    Abstract: It is an object of the invention to provide a substrate processing equipment that can predict a temperature of a substrate and easily control temperature of the substrate. Formed in a reactor (processing chamber) 3 are four temperature adjustment zones, of which setting and adjustment of temperature can be made by zone heaters 340-1 to 340-4. A temperature controller 4 mixes temperatures detected by inner thermocouples 302-1 to 302-4 and outer thermocouples 342-1 to 342-4 to calculate predicted temperatures of substrates by means of the first-order lag calculation on the basis of time constants of temperatures of substrates heated by the zone heaters 340-1 to 340-4. Also, the temperature controller 4 calculates electric power values (operating variables) for the zone heaters 340-1 to 340-4 with the use of predicted temperatures of substrates to output the same to the zone heaters 340-1 to 340-4.
    Type: Application
    Filed: June 18, 2004
    Publication date: August 24, 2006
    Inventors: Kazuo Tanaka, Masaaki Ueno, Masashi Sugishita
  • Patent number: 7091767
    Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: August 15, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kazuo Tanaka, Hiroyuki Mizuno, Rie Nishiyama, Manabu Miyamoto
  • Publication number: 20060162316
    Abstract: Techniques suitable for recovering energy from a high-temperature gas of an ordinary pressure are provided. A turbomachine has a turbine 16 and compressors 20 and 24. A combustor 12 is disposed at a stage above the turbine 16. A power generating system generates power by passing a working fluid for the turbomachine through the combustor 12, the turbine 16 and the compressors 20 and 24 in that order.
    Type: Application
    Filed: October 3, 2003
    Publication date: July 27, 2006
    Applicants: Kawasaki Jokogyo Kabushiki Kaisha, National Institute of advanced Industrial Science and Technology
    Inventors: Kazuo Tanaka, Seiji Yamashita, Eiichi Harada, Norihiko Iki, Sanyo Takahashi, Hirohide Furutani
  • Patent number: 7065297
    Abstract: In each node of an optical transmission system: an optical preamplifier has an ALC function for maintaining an optical output level constant and an AGC function for maintaining the gain constant; the operational mode of the optical preamplifier is changed from an ALC mode to an AGC mode after the gain is set in the ALC mode; an optical postamplifier has an AGC function; an optical switch unit performs an optical crossconnect operation; and a thru-light-shutoff control unit makes a switch setting so as to shut off pass-through light in the optical switch unit and stop transmission of an optical signal having an unstable level to a next stage when the optical preamplifier operates in the ALC mode, and clears the switch setting when the operational mode of the optical preamplifier is changed to the AGC mode.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: June 20, 2006
    Assignee: Fujitsu Limited
    Inventors: Kazunori Horachi, Taro Asao, Kazuo Tanaka, Nobuyuki Nemoto, Hiroyuki Matsumoto, Miwa Taniguchi, Toshihiro Suzuki, Manabu Suzuki
  • Publication number: 20060087781
    Abstract: The present invention is provided to suppress occurrence of an erroneous operation in a protection circuit due to a relatively small power source fluctuation such as a power source noise. The protection circuit has a first resistor and a capacitor connected in series between a power source line and a ground line, an inverter whose input is connected between the first resistor and the capacitor, and a MOS transistor whose gate electrode receives an output of the inverter and whose drain electrode and source electrode are connected to the power source line and the ground line. When a high voltage fluctuation occurs in the power source line, a level change at a connection point between the first resistor and the capacitor is delayed according to a time constant. By the delay, the MOS transistor that receives an output of the inverter is temporarily turned on and discharges a high voltage to the ground line.
    Type: Application
    Filed: October 20, 2005
    Publication date: April 27, 2006
    Inventors: Hiroyasu Ishizuka, Kazuo Tanaka
  • Publication number: 20060077601
    Abstract: The invention intends to provide a semiconductor device capable of preventing an electrostatic breakdown especially by the CDM, of the electrostatic breakdowns generated between plural power supply systems, with a few number of protection circuits. The semiconductor device includes a first circuit block that operates with a first power supply voltage and a first reference voltage, and a second circuit block that operates with a second power supply voltage and a second reference voltage. Further, the semiconductor device includes a first clamp circuit that clamps a potential between the first power supply voltage and the second reference voltage, a second clamp circuit that clamps a potential between the second power supply voltage and the first reference voltage, and a third clamp circuit that clamps a potential between the first reference voltage and the second reference voltage.
    Type: Application
    Filed: September 12, 2005
    Publication date: April 13, 2006
    Inventors: Hiroyuki Ikeda, Kazuo Tanaka, Hiroyasu Ishizuka, Koichiro Takakuwa
  • Patent number: 7002734
    Abstract: A WDM optical transmission apparatus is disclosed utilizing ASE light. The WDM optical transmission apparatus includes a pre-amplifier having two control modes consisting of ALC mode in which the gain of an optical amplifier is controlled such that the total output of the optical amplifier is constant for a multiplexed wavelength number n, and of AGC mode which is a control mode maintaining constant the ratio of an optical input level to an optical output level for the multiplexed wavelength number n; and a post-amplifier having two control modes consisting of ASE mode in which the gain of the post-amplifier is set higher than that in the AGC mode and is set such that the output level of ASE light corresponds to the multiplexed wavelength number n, and of the AGC mode; wherein in the ASE mode, the gain of the pre-amplifier in the WDM optical transmission apparatus at the next node is set under an ALC control utilizing ASE light output from the post-amplifier.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: February 21, 2006
    Assignee: Fujitsu Limited
    Inventors: Kazunori Horachi, Taro Asao, Nobuyuki Nemoto, Kazuo Tanaka
  • Patent number: 6977771
    Abstract: The gain control circuit controls the amplification ratio of EDFA based on the results of having measured the input power monitor which monitors the EDFA input optical level which amplifies light and of having measured the output power monitor which monitors the output optical level. The optical pre-amplifier receives a notice of the number of wavelengths from a fore node and a notice of whether the optical post-amplifier of a fore node is in normal operation by a supervisory control signal, and changes over the gain control circuit to either the ALC or AGC mode. When the number of wavelengths changes while the optical pre-amplifier is operating in the ALC mode, the optical pre-amplifier is controlled in the AGC mode using the backed-up amplifier gain. Also, the gain value when the optical pre-amplifier is in routine operation is backed up in an amplifier gain back-up unit and an back-up unit.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: December 20, 2005
    Assignee: Fujitsu Limited
    Inventors: Taro Asao, Nobuyuki Nemoto, Kazuo Tanaka, Kazunori Horachi
  • Publication number: 20050266685
    Abstract: In a method for controlling temperatures in a semiconductor manufacturing apparatus including a reaction chamber and a plurality of heating sources, a set of power ratios to be fed to the heating sources is determined for each of two or more selected temperatures. Then, a temperature of the reaction chamber is controlled by performing power control on the heating sources based on at least one set of power ratios obtained.
    Type: Application
    Filed: June 15, 2005
    Publication date: December 1, 2005
    Inventors: Minoru Nakano, Masaaki Ueno, Kazuo Tanaka
  • Publication number: 20050266797
    Abstract: The present invention is directed to a wireless communication system capable of keeping a level of a wireless signal received by a relay apparatus (20) within a predetermined dynamic range. In a control apparatus (10), a transmitting section (102) converts a downstream electric signal into a downstream optical signal and transmits the downstream optical signal to the relay apparatus (20) via an optical transmission path (40). The relay apparatus (20) converts the received downstream optical signal into a downstream electric signal and transmits the downstream electric signal as a wireless signal to a wireless communication terminal (30) from a transmitting/receiving antenna section (204). In the relay apparatus (20), a level adjustment section (207) adjusts the level of the wireless signal transmitted by the relay apparatus (20) such that the receiving level of the wireless signal received by the relay apparatus is kept within a predetermined range.
    Type: Application
    Filed: July 22, 2004
    Publication date: December 1, 2005
    Inventors: Kuniaki Utsumi, Hiroaki Yamamoto, Kouichi Masuda, Tsutomu Niiho, Mariko Nakaso, Kazuo Tanaka, Hiroyuki Sasai
  • Patent number: 6947634
    Abstract: An optical waveguide device increases the intensity of light transmitted through an optical waveguide for a reduced cost without expanding the area of the light. The optical waveguide device according to the present invention includes an optical waveguide and defining surfaces defining the optical waveguide. The defining surfaces are formed of plasmon activating medium. The defining surface include a pair of inner parts that face each other along a direction perpendicular to a light transmission direction. The distance between the inner parts is less than the half of the wavelength of the light transmitted through the optical waveguide.
    Type: Grant
    Filed: July 25, 2003
    Date of Patent: September 20, 2005
    Assignee: Gifu University
    Inventors: Kazuo Tanaka, Masahiro Tanaka
  • Publication number: 20050142554
    Abstract: A nucleic acid base for hole transportation in DNAs which does not cause oxidative decomposition; and an artificial DNA molecule which can realize effective hole transportation in DNAs while maintaining the double spiral structure of the DNAs. Provided are: a nucleic acid which contains a benzodeazaadenine derivative base represented by the general formula (I): (wherein R1, R2, R3, R4, R5, and R6 each independently represents hydrogen, amino, mono (lower alkyl) amino, di (lower alkyl) amino, hydroxy, lower alkoxy, halogeno, cyano, mercapto, lower alkylthio, or aryl; and R7 and R8 each independently represents hydrogen or a group bonded to phosphoric acid); and a polynucleotide comprising the nucleic acid.
    Type: Application
    Filed: August 15, 2002
    Publication date: June 30, 2005
    Inventors: Isao Saito, Akimitsu Okamoto, Kazuo Tanaka