Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer.

Abstract: An image forming apparatus is provided that includes an image forming unit disposed in a main body and configured to form an image on a recording medium, an output tray provided in the main body and configured to receive the recording medium having an image formed thereon, and an ejection device provided in the main body and configured to eject the recording medium to the output tray. The apparatus may further include a movable sheet guiding member movably attached to the main body and a stationary sheet guiding member disposed downstream of the movable sheet guiding member in a recording medium ejection direction and above the output tray. The movable sheet guiding member can press a recording medium ejected from the ejection device downward, and the stationary sheet guiding member can protrude from the main body.

Abstract: A sheet conveying device to convey a sheet in a sheet path is provided. The sheet conveying device includes a separator roller, which is arranged to be rotatably in contact with the sheet to apply conveying force to the sheet, a pad assembly including a separator pad, which is arranged to be in contact with the sheet stack to apply convey resistance to the sheet stack, and a holder, which is swingably attached to a base member and holds the separator pad, the base member being in a fixed position with respect to the separator roller, a spring, which urges the pad assembly toward the separator roller, and a slidable member, which is attached to the pad assembly to be integrally movable with the pad assembly and to be slidably in contact with a first slidable section in the base member.

Abstract: In a DC-DC converter, a multilayer wiring layer is provided on a silicon substrate, and a control circuit configured to control an input circuit and an output circuit is formed in the silicon substrate and the multilayer wiring layer. Moreover, a sealing resin layer covering the multilayer wiring layer and a connecting member connected to an uppermost wiring of the multilayer wiring layer, penetrating the sealing resin layer and having an upper end portion protruding from an upper surface of the sealing resin layer are provided. The upper end portion of the connecting member is formed from a protruding electrode. Horizontal cross-sectional area of the connecting member connected to terminals of the output circuit is larger than horizontal cross-sectional area of the connecting member connected to terminals of the control circuit.

Abstract: According to one embodiment, a DC-DC converter includes a mounting substrate and a semiconductor device. The semiconductor device includes a first switch element, a second switch element, a first interconnect layer receiving an input potential, a second interconnect layer connected with an inductor, a third interconnect layer receiving a reference potential, and a fourth interconnect layer connected with the inductor. These layers are disposed side by side in one direction on one layer. The mounting substrate includes a fifth interconnect pattern receiving an input potential and disposed adjacently on one side of a mounting region of the semiconductor device, a sixth interconnect pattern receiving a reference voltage and disposed adjacently on the one side of the mounting region, and a seventh interconnect pattern disposed adjacently on one other side opposite to the one side of the mounting region.

Abstract: According to one embodiment, a power semiconductor system includes; a first power semiconductor element, a driver IC, a first temperature detection element, a control circuit and an overheat protection control section. The first power semiconductor element controls current flowing between a first electrode and a second electrode with a control electrode. The driver IC supplies a drive signal making the first power semiconductor element on and off. The first temperature detection element detects a temperature of the driver IC. The control circuit supplies a control signal for controlling operation of the driver IC to the driver IC. The overheat protection control section is configured to supply an overheat protection signal to the control circuit based on an output of the first temperature detection element. The control circuit performs overheat protection operation. The overheat protection control section supplies the overheat protection signal to the control circuit.

Abstract: A DC-DC converter includes a high side transistor and a low side transistor connected in series between an input potential and a grounding potential, and an LC filter connected between a connection point of the both transistors and an output terminal. A control unit controls the gate potential of the high side transistor in an ON state and the gate potential of the low side transistor in an ON state according to a magnitude of a current output from the output terminal.

Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.

Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer.

Abstract: According to one embodiment, a semiconductor device includes a base layer of a second conductivity type, a device isolation layer, a control electrode, a high dielectric layer, a first main electrode, and a second main electrode. The base layer includes a source region of a first conductivity type and a drain region of the first conductivity type. The source region and the drain region are selectively formed on a surface of the base layer. The device isolation layer is provided in the base layer to be extended in a direction from the source region to the drain region. The control electrode is provided on a top side of the device isolation layer to control a current passage between the source region and the drain region. The high dielectric layer is arranged in at least a part on a top side of the base layer or in at least a part in the device isolation layer. The high dielectric layer has a higher dielectric constant than a dielectric constant of the device isolation layer.

Abstract: According to one embodiment, a semiconductor device includes a first switching element and a second switching element. The first switching element has a first threshold voltage and a first gate electrode connected to a first gate wiring. The second switching element has a second threshold voltage and a second gate electrode connected to a second gate wiring. The second threshold voltage has a larger absolute value than the first threshold voltage. The second gate wiring has a larger resistance per unit length than the first gate wiring.

Abstract: According to one embodiment, a semiconductor package includes a chip, a plurality of bumps, a source frame, a drain frame, and a mold member. The chip has a lateral transistor formed inside the chip and has a top source electrode exposed on a first surface of the chip and a top drain electrode exposed on the first surface of the chip. The plurality of bumps are mounted on each of the top source electrode and the top drain electrode. The source frame is connected to the top source electrode through the bumps. The drain frame is connected to the top drain electrode through the bumps. The mold member embeds at least a part of each of the chip, the bumps, the source frame and the drain frame.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate of a first conductivity type, an element isolation insulator, a source layer of a second conductivity type, a drain layer of the second conductivity type, a contact layer of the first conductivity type and a gate electrode. The element isolation insulator is formed on the semiconductor substrate. The source layer is formed on the semiconductor substrate and is in contact with a side surface of the element isolation insulator. The drain layer is formed on the semiconductor substrate, is in contact with the side surface, and is spaced from the source layer. The contact layer is formed between the source layer and the drain layer. The gate electrode is provided on the element isolation insulator along the side surface.

Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.

Abstract: A semiconductor device comprises a semiconductor substrate of the first conductivity type. A well layer of the first conductivity type is selectively formed on the semiconductor substrate. A first diffused layer of the second conductivity type is selectively formed on the well layer. A second diffused layer of the second conductivity type is formed on the well layer apart from the first diffused layer. A control electrode is formed on an insulating film between the first diffused layer and the second diffused layer. A main electrode is formed on each of the first diffused layer and the second diffused layer. A first trench is formed in the semiconductor substrate surrounding the well layer. A third diffused layer of the second conductivity type is formed contacting to the first trench. The second diffused layer and the third diffused layer are electrically kept at the same potential.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer.

Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.

Abstract: According to one embodiment, a semiconductor apparatus includes a substrate, a semiconductor layer of a first conductivity type, a first semiconductor region of a second conductivity type, a first main electrode, a second semiconductor layer of the second conductivity type, a third semiconductor layer of the first conductivity type, a second main electrode, a gate insulating film, and a gate electrode. An electron injected from the first semiconductor region into the semiconductor layer is recombined with an electron hole injected from the third semiconductor region into the semiconductor layer in a state of a body diode is biased in a forward direction. The body diode includes the semiconductor layer, the first semiconductor region, and the third semiconductor region.