Patents by Inventor Kazutoshi Nakamura
Kazutoshi Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7863707Abstract: A semiconductor device includes, in one semiconductor substrate: a plurality of switching elements connected between a terminal of an input voltage and an inductor; a driver circuit connected to a gate electrode of the switching element and driving the switching element; a reference voltage line connected to a source electrode of the switching element; a power supply line of the driver circuit; and a capacitor connected between the power supply line and the reference voltage line.Type: GrantFiled: May 15, 2008Date of Patent: January 4, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Kazutoshi Nakamura
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Publication number: 20100140715Abstract: A semiconductor device includes: a semiconductor region of first conductivity type provided in a semiconductor layer of first conductivity type; a first semiconductor region of second conductivity type; a second semiconductor region of second conductivity type; a third semiconductor region of second conductivity type having a lower impurity concentration than the second semiconductor region of second conductivity type; a first insulating layer provided in the third semiconductor region of second conductivity type; a control electrode provided on the semiconductor region of first conductivity type via a second insulating layer; a first auxiliary electrode provided on the first insulating layer; a first main electrode electrically connected to the first semiconductor region of second conductivity type; and a second main electrode electrically connected to the second semiconductor region of second conductivity type.Type: ApplicationFiled: December 3, 2009Publication date: June 10, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazutoshi Nakamura, Norio Yasuhara
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Patent number: 7719053Abstract: A semiconductor device comprises a semiconductor region of the first conduction type. A first main electrode is connected to the semiconductor region. A base region of the second conduction type is formed on the semiconductor region. A diffused region of the first conduction type is formed on the base region. A second main electrode is connected to the diffused region and the base region. A first trench is formed extending from a surface of the diffused region to the semiconductor region. A second trench is formed from the first trench deeper than the first trench. A gate electrode is formed on a side of the first trench via a first insulator film. A protruded electrode is formed in the second trench via a second insulator film as protruded lower than the gate electrode.Type: GrantFiled: December 8, 2006Date of Patent: May 18, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Kazutoshi Nakamura
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Patent number: 7675757Abstract: Disclosed is a DC-DC converter including: a first switching element ON/OFF controlling a current fed from a primary side to a secondary side; a second switching element provided in parallel to the first switching element, controlled at a substantially same timing as an ON/OFF timing of the first switching element and being lower in current rating than the first switching element; and a resistance inserted and connected between a node of a primary side of the second switching element and the primary side of the first switching element.Type: GrantFiled: June 6, 2006Date of Patent: March 9, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Kazutoshi Nakamura
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Patent number: 7663186Abstract: A semiconductor device includes: a substrate, a surface portion thereof serving as a drain layer; a first main electrode connected to the drain layer; an epitaxial layer formed on the drain layer; a base layer formed on the epitaxial layer; a source layer formed in a base layer surface portion; an insulated trench sandwiched by base layers; a JFET layer formed on trench side walls; an LDD layer formed in a base layer surface portion and connected to the JFET layer around a top face of the trench; a control electrode formed on a gate insulating film formed on an LDD layer surface part, on surfaces of source layer end parts facing each other across the trench, and on a base layer region sandwiched by the LDD and source layers; and a second main electrode connected to the source and base layers sandwiching the control electrode.Type: GrantFiled: May 9, 2008Date of Patent: February 16, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Syotaro Ono, Yoshihiro Yamaguchi, Yusuke Kawaguchi, Kazutoshi Nakamura, Norio Yasuhara, Kenichi Matsushita, Shinichi Hodama, Akio Nakagawa
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Publication number: 20100013451Abstract: A semiconductor device includes: a high-side switching element having a first switching element connected between an input voltage line and an inductive load; and a low-side switching element having a second switching element and a third switching element that are connected in parallel between the inductive load and a reference voltage line. A surge current is discharged through the third switching element to the reference voltage line when a surge is applied to a terminal connected to the inductive load in the low-side switching element.Type: ApplicationFiled: July 9, 2009Publication date: January 21, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazutoshi Nakamura, Norio Yasuhara
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Publication number: 20100006936Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer.Type: ApplicationFiled: June 1, 2009Publication date: January 14, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomoko Matsudai, Norio Yasuhara, Kazutoshi Nakamura
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Publication number: 20090295341Abstract: A DC-DC converter includes a high side transistor and a low side transistor connected in series between an input potential and a grounding potential, and an LC filter connected between a connection point of the both transistors and an output terminal. A control unit controls the gate potential of the high side transistor in an ON state and the gate potential of the low side transistor in an ON state according to a magnitude of a current output from the output terminal.Type: ApplicationFiled: May 28, 2009Publication date: December 3, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazutoshi Nakamura, Toshiyuki Naka
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Publication number: 20090243087Abstract: In a DC-DC converter, a multilayer wiring layer is provided on a silicon substrate, and a control circuit configured to control an input circuit and an output circuit is formed in the silicon substrate and the multilayer wiring layer. Moreover, a sealing resin layer covering the multilayer wiring layer and a connecting member connected to an uppermost wiring of the multilayer wiring layer, penetrating the sealing resin layer and having an upper end portion protruding from an upper surface of the sealing resin layer are provided. The upper end portion of the connecting member is formed from a protruding electrode. Horizontal cross-sectional area of the connecting member connected to terminals of the output circuit is larger than horizontal cross-sectional area of the connecting member connected to terminals of the control circuit.Type: ApplicationFiled: March 20, 2009Publication date: October 1, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazutoshi NAKAMURA, Nario YASUHARA, Tomoko MATSUDAI, Daisuke MINOHARA
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Patent number: 7579669Abstract: A semiconductor device comprises a high side switching element, a driver circuit, and a low side switching element. The high side switching element is formed on a first semiconductor substrate, has a current path to one end of which an input voltage is supplied, and the other end of the current path is connected to an inductance. The driver circuit is formed on the first semiconductor substrate, on which the high side switching element is formed, and drives the high side switching element. The low side switching element is formed on a second semiconductor substrate separate from the first semiconductor substrate, and has a drain connected to the inductance and a source supplied with a reference potential.Type: GrantFiled: October 16, 2006Date of Patent: August 25, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Kazutoshi Nakamura, Norio Yasuhara, Tomoko Matsudai, Kenichi Matsushita, Akio Nakagawa
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Publication number: 20090179681Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.Type: ApplicationFiled: January 9, 2009Publication date: July 16, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazutoshi Nakamura, Toru Takayama, Yuki Kamata, Akio Nakagawa, Yoshinobu Sano, Toshiyuki Naka
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Patent number: 7557545Abstract: An electronic power unit includes first and second MOS transistors and a digital control circuit. The first MOS transistor applies a voltage to the load. The second MOS transistor remains on while the first MOS transistor remains off and rectifies the current flowing in the load. The digital control circuit turns on the first transistor upon lapse of a first time interval from the time the second MOS transistor is turned off. The digital control circuit turns on the second MOS transistor upon lapse of a second time interval from the time the first MOS transistor is turned off. The digital control circuit controls the on-period of the first MOS transistor so that the voltage applied to the load is constant in a discontinuous conduction mode. The digital control circuit determines, while the voltage applied to the load is constant, an optimal value of the first time from the duty.Type: GrantFiled: July 13, 2006Date of Patent: July 7, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Toshiyuki Naka, Akio Nakagawa, Kazutoshi Nakamura
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Patent number: 7554160Abstract: A semiconductor device has a source region, a channel region and a drain region formed in order along a surface of a substrate, a vertical type bipolar transistor formed from the source region below the substrate, a base contact region of the vertical type bipolar transistor, a buried layer connected to the vertical type bipolar transistor, a buried contact layer which electrically conducts the drain region and the buried layer and a drift region formed between the drain region and the channel region, which has the same conductive type as that of the drain region and has impurity concentration less than that of the drain region.Type: GrantFiled: January 18, 2006Date of Patent: June 30, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Kazutoshi Nakamura
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Publication number: 20080283965Abstract: A semiconductor device includes, in one semiconductor substrate: a plurality of switching elements connected between a terminal of an input voltage and an inductor; a driver circuit connected to a gate electrode of the switching element and driving the switching element; a reference voltage line connected to a source electrode of the switching element; a power supply line of the driver circuit; and a capacitor connected between the power supply line and the reference voltage line.Type: ApplicationFiled: May 15, 2008Publication date: November 20, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Kazutoshi Nakamura
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Publication number: 20080251838Abstract: A semiconductor device includes: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; an insulating layer formed in the trench; an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the firstType: ApplicationFiled: May 9, 2008Publication date: October 16, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Syotaro Ono, Yoshihiro Yamaguchi, Yusuke Kawaguchi, Kazutoshi Nakamura, Norio Yasuhara, Kenichi Matsushita, Shinichi Hodama, Akio Nakagawa
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Patent number: 7432579Abstract: A MOS field-effect transistor includes a semiconductor substrate of a first-conductivity type, a semiconductor layer of the first-conductivity type, a source region of a second-conductivity type, a first drain region of the second-conductivity type, a resurf layer of the second-conductivity type provided in the surface of the semiconductor layer between the source region and the first drain region in contact with the first drain region, and having a lower impurity concentration than the first drain region, a gate insulation film, and a gate electrode provided on the gate insulation film between the source region and resurf layer. A Schottky barrier diode includes a second drain region of the second-conductivity type provided in the surface of the semiconductor layer separate from the first drain region in a direction away from the gate electrode, and a Schottky electrode provided on the semiconductor layer between the first and second drain regions.Type: GrantFiled: October 7, 2004Date of Patent: October 7, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Tomoko Matsudai, Kazutoshi Nakamura, Akio Nakagawa
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Publication number: 20080128828Abstract: A semiconductor device comprises a semiconductor substrate of the first conductivity type. A well layer of the first conductivity type is selectively formed on the semiconductor substrate. A first diffused layer of the second conductivity type is selectively formed on the well layer. A second diffused layer of the second conductivity type is formed on the well layer apart from the first diffused layer. A control electrode is formed on an insulating film between the first diffused layer and the second diffused layer. A main electrode is formed on each of the first diffused layer and the second diffused layer. A first trench is formed in the semiconductor substrate surrounding the well layer. A third diffused layer of the second conductivity type is formed contacting to the first trench. The second diffused layer and the third diffused layer are electrically kept at the same potential.Type: ApplicationFiled: November 30, 2007Publication date: June 5, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Kazutoshi NAKAMURA
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Publication number: 20070246770Abstract: A semiconductor device, including a semiconductor region of the first conduction type which is formed on a semiconductor substrate; a gate electrode at least part of which is present within a trench which is selectively formed in part of the semiconductor region, and an extended top end portion of which is formed to have a wide width via a stepped portion; a gate insulating film which is formed between the trench and the gate electrode along a wall surface of the trench; a base layer of the second conduction type which is provided on the semiconductor region via the gate insulating film so as to enclose a side wall except a bottom portion of the trench; a source region of the first conduction type which is formed adjacent to the gate insulating film outside the trench in the vicinity of a top surface of the base layer; and an insulating film which is formed at least partially between a bottom surface of the top end portion and a top surface of the source region and which is formed so as to have a film thickneType: ApplicationFiled: June 26, 2007Publication date: October 25, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazutoshi NAKAMURA, Syotaro Ono
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Patent number: 7253473Abstract: A semiconductor device includes: a semiconductor substrate of the first-type; a semiconductor region of the first-type formed on the substrate; a gate electrode a part of which is present within a trench selectively formed in part of the semiconductor region, and an extended top-end to have a wide width via a stepped-portion; a gate insulating-film formed between the trench and the gate electrode along a wall surface of the trench; a base layer of the second-type on the region via the film to enclose a side-wall except a bottom of the trench; a source region of the first-type adjacent to the film outside the trench in the vicinity of a top surface of the base layer; and an insulating-film formed partially between a bottom-surface of the top-end and a top-surface of the source region and formed to have a thickness larger than that of the gate insulating-film within the trench.Type: GrantFiled: October 7, 2005Date of Patent: August 7, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Kazutoshi Nakamura, Syotaro Ono
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Publication number: 20070138547Abstract: A semiconductor device comprises a semiconductor region of the first conduction type. A first main electrode is connected to the semiconductor region. A base region of the second conduction type is formed on the semiconductor region. A diffused region of the first conduction type is formed on the base region. A second main electrode is connected to the diffused region and the base region. A first trench is formed extending from a surface of the diffused region to the semiconductor region. A second trench is formed from the first trench deeper than the first trench. A gate electrode is formed on a side of the first trench via a first insulator film. A protruded electrode is formed in the second trench via a second insulator film as protruded lower than the gate electrode.Type: ApplicationFiled: December 8, 2006Publication date: June 21, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Kazutoshi Nakamura