Patents by Inventor Kazuya Kobayashi

Kazuya Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11515439
    Abstract: A photovoltaic device includes: a semiconductor substrate stretching in a first direction and a second direction that intersects the first direction; and a first amorphous semiconductor film and a second amorphous semiconductor film both provided on the semiconductor substrate. The second amorphous semiconductor film has a differ conductivity type from the first amorphous semiconductor film. The first amorphous semiconductor film and the second amorphous semiconductor film are divided into a plurality of sections in the first direction and the second direction.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: November 29, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Teruaki Higo, Chikao Okamoto, Naoki Asano, Masamichi Kobayashi, Natsuko Fujiwara, Rihito Suganuma, Toshihiko Sakai, Kazuya Tsujino, Liumin Zou
  • Publication number: 20220367832
    Abstract: The present disclosure provides a front panel for a display device comprising a substrate layer, an A layer, an impact absorbing layer, and a B layer, in this order, wherein a shear storage elastic modulus of the A layer and the B layer, at frequency of 950 Hz and temperature of 23° C., is 20 MPa or less, and in the impact absorbing layer, a tensile storage elastic modulus at frequency of 950 Hz and temperature of 23° C. is 200 MPa or more and 5000 MPa or less, and a glass transition temperature is 50° C. or more.
    Type: Application
    Filed: September 28, 2020
    Publication date: November 17, 2022
    Inventors: Atsuhiro KOBAYASHI, Yousuke KOUSAKA, Takayuki FUKUDA, Kazuya HONDA, Kana YAMAMOTO, Yoshimasa OGAWA, Jun SATO, Gen FURUI, Keisuke YAMADA, Saori KAWAGUCHI
  • Publication number: 20220328694
    Abstract: Provided is a semiconductor device in which deterioration of electric characteristics which becomes more noticeable as the semiconductor device is miniaturized can be suppressed. The semiconductor device includes a first oxide film, an oxide semiconductor film over the first oxide film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a second oxide film over the oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film over the second oxide film, and a gate electrode in contact with the gate insulating film. A top end portion of the oxide semiconductor film is curved when seen in a channel width direction.
    Type: Application
    Filed: June 21, 2022
    Publication date: October 13, 2022
    Inventors: Kazuya HANAOKA, Daisuke MATSUBAYASHI, Yoshiyuki KOBAYASHI, Shunpei YAMAZAKI, Shinpei MATSUDA
  • Publication number: 20220306090
    Abstract: A stop assist system for moving a moving body to a stop position and making the moving body stop at the stop position includes: an external environment recognizing unit that recognizes an external environment of the moving body; and a moving body control unit that executes a driving process to make the moving body travel to the stop position based on a recognition result of the external environment recognizing unit. The moving body control unit suspends the driving process when, while the moving body is traveling to the stop position, the moving body control unit determines, based on the recognition result, that there is an object within a range of a prescribed lateral threshold value on a lateral outside of the moving body and the object extends over a prescribed longitudinal threshold value or more along a travel direction within the range.
    Type: Application
    Filed: February 18, 2022
    Publication date: September 29, 2022
    Inventors: Junpei NOGUCHI, Gaku SHIMAMOTO, Takuma SEKINO, Tatsuro FUJIWARA, Akiko NAKAMURA, Kazuya KOBAYASHI, Masafumi SAGARA, Takeshi SASAJIMA
  • Patent number: 11441667
    Abstract: A continuously variable transmission includes a variator having a belt wound around a pair of pulleys, and a case forming a container chamber for the variator. The pulleys include fixed pulleys and movable pulleys. The belt includes elements stacked to be arranged in an annular form, and rings binding the element stacked. A circumference wall portion of the case is provided with a monitoring hole enabling flank faces of the elements to be monitored.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: September 13, 2022
    Assignee: JATCO LTD
    Inventors: Kazuyoshi Kobayashi, Masao Arimatsu, Masayuki Furuya, Kenichi Yamamoto, Shogo Fujii, Masakazu Tamura, Kazuya Numata, Hirohisa Yukawa
  • Patent number: 11434421
    Abstract: A phosphor which has a main crystal phase having the same crystal structure as that of CaAlSiN3, wherein the phosphor satisfies conditions of a span value (d90?d10)/d50 of 1.70 or less and a d50 of 10.0 ?m or less, as represented with d10, d50, and d90 on a volume frequency measured according to a laser diffraction method; wherein the d10, d50, and d90 on a volume frequency in a particle distribution measured are each a measured by loading 0.5 g of a phosphor into 100 ml of a solution of 0.05% by weight of sodium hexametaphosphate mixed in ion exchange water, and subjecting the resultant to a dispersing treatment for 3 minutes with an ultrasonic homogenizer at an oscillation frequency of 19.5±1 kHz, a chip size of 20?, and an amplitude of vibration of 32±2 ?m, with a chip placed at a central portion.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: September 6, 2022
    Assignee: DENKA COMPANY LIMITED
    Inventors: Kazuya Sugita, Yusuke Takeda, Keita Kobayashi, Akihisa Kajiyama
  • Patent number: 11430894
    Abstract: Provided is a semiconductor device in which deterioration of electric characteristics which becomes more noticeable as the semiconductor device is miniaturized can be suppressed. The semiconductor device includes a first oxide film, an oxide semiconductor film over the first oxide film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a second oxide film over the oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film over the second oxide film, and a gate electrode in contact with the gate insulating film. A top end portion of the oxide semiconductor film is curved when seen in a channel width direction.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: August 30, 2022
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kazuya Hanaoka, Daisuke Matsubayashi, Yoshiyuki Kobayashi, Shunpei Yamazaki, Shinpei Matsuda
  • Publication number: 20220260684
    Abstract: [Object] To provide a light-emitting element that has a vertical-cavity surface-emitting laser structure and is suitable for a long-distance light irradiation, and a ranging apparatus. [Solving Means] A light-emitting element according to the present technology includes a plurality of light emitters, a first electrode terminal, and a second electrode terminal. The plurality of light emitters is a plurality of light emitters one-dimensionally or two-dimensionally arranged in a direction that is vertical to an optical axis corresponding to light that exits each of the plurality of light emitters, each of the plurality of light emitters being a vertical-cavity surface-emitting laser element, each of the plurality of light emitters including a first electrode and a second electrode, each of the plurality of light emitters emitting the light due to current flowing from the first electrode to the second electrode. The first electrode terminal is electrically connected to the first electrode.
    Type: Application
    Filed: July 15, 2020
    Publication date: August 18, 2022
    Inventors: TAKASHI KOBAYASHI, KAZUYA WAKABAYASHI, MOTOI KIMURA, TATSUYA OIWA
  • Patent number: 11414746
    Abstract: A film forming apparatus includes a base material support mechanism configured to rotate a base material supported by the base material support mechanism about a first axis, and a first cathode portion on which a target in a cylindrical shape containing a film forming material is mounted and configured to rotate the target about a second axis, in a chamber. The second axis is disposed at a position skewed with respect to the first axis.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: August 16, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kazuya Demura, Takamasa Horie, Hiroyuki Kobayashi
  • Publication number: 20220252762
    Abstract: Provided is a coating member having improved both in anti-reflection property and design property. The present invention provides a coating member comprising a substrate layer and an optical interference layer formed from an optical interference layer-forming composition, wherein the optical interference layer is disposed on at least a part of a viewing side surface of the substrate layer, the optical interference layer is in a range of more than 0 nm and less than or equal to 600 nm, the optical interference layer has a relationship of 0.08<(a refractive index of the substrate layer)?(a refractive index of the optical interference layer)<0.45, the optical interference layer-forming composition is a composition for inkjet coating, and the optical interference layer is an optical interference layer formed by an inkjet method.
    Type: Application
    Filed: May 19, 2020
    Publication date: August 11, 2022
    Applicant: NIPPON PAINT AUTOMOTIVE COATINGS CO., LTD.
    Inventors: Kazuhito KOBAYASHI, Takeki HOSOKAWA, Takuma OKADA, Kazuya TAKAHASHI
  • Patent number: 11404357
    Abstract: A dielectric film is disposed on a semiconductor substrate, and a conductor including a bent section is arranged between the semiconductor substrate and the dielectric film. A pad is disposed on the dielectric film. The pad is covered with a protective film. The protective film has an opening through which an upper surface of the pad is exposed. The bent section in the conductor and the pad overlap each other as seen in plan view, and an inside corner and an outside corner in the bent section are chamfered.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: August 2, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi Kurokawa, Hiroaki Tokuya, Kazuya Kobayashi, Yuichi Sano
  • Publication number: 20220237335
    Abstract: An object of the present invention is to provide a facility state analysis apparatus, a facility state analysis method, and a program capable of extracting a pole having a high risk without an inspector visiting a site. The facility state analysis apparatus according to the present invention creates a pole model from a material characteristic, dimensions, and a structure model of a pole, highly accurately estimates, by using a finite element method, a facility state such as deflection and an inclination when tension by a separately created cable model is applied to the pole model, and visualizes strength remaining in a facility system.
    Type: Application
    Filed: June 3, 2019
    Publication date: July 28, 2022
    Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Masaki WAKI, Kazuya ANDO, Gen KOBAYASHI, Ryoichi KANEKO, Hiroaki TANIOKA
  • Publication number: 20220231462
    Abstract: A connector includes a female terminal module and a male terminal module that is to be coupled to the female terminal module. The female terminal module includes a female-side inner conductor, a female-side derivative, and a female-side outer conductor. The female-side outer conductor receives therein the female-side inner conductor via the female-side derivative. The male terminal module includes a male-side inner conductor, a male-side derivative, and a male-side outer conductor. The male-side outer conductor receives therein the male-side inner conductor via the male-side derivative and is connected to the female-side outer conductor. The female-side fitting portion of the female-side derivative and the male-side fitting portion of the male-side derivative are fitted to each other with recess-protrusion fitting. The male-side inner conductor includes a male connection portion and the male connection portion is inserted in the female-side fitting portion and connected to the female-side inner conductor.
    Type: Application
    Filed: June 5, 2020
    Publication date: July 21, 2022
    Applicants: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yorikazu MURABAYASHI, Hiroyuki KODAMA, Kazuya KOBAYASHI, Suguru YAMAGISHI, Toyohisa TAKANO
  • Patent number: 11377594
    Abstract: A ?-type sialon phosphor represented by the following expression 1, in which D50 is 10 ?m or less, and values of D10, D50, and D90 satisfy a relationship of the following expression 2 with respect to D10, D50, and D90 (each unit is [?m]) on a volume frequency basis as measured according to a laser diffraction/scattering method. Expression 1: Si12-aAlaObN16-b:Eux (wherein 0<a?3; 0<b?3; 0<x?0.1), expression 2: (D90?D10)/D50<1.6 (wherein the D10, D50, and D90 (each unit is [?m]) on a volume frequency basis as measured according to the laser diffraction/scattering method.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: July 5, 2022
    Assignee: DENKA COMPANY LIMITED
    Inventors: Keita Kobayashi, Shunsuke Mitani, Ryousuke Kondo, Kazuya Sugita, Takuya Matsufuji, Akihisa Kajiyama
  • Patent number: 11374162
    Abstract: A piezoelectric element includes a first electrode; a piezoelectric layer, placed on or above the first electrode, containing potassium, sodium, niobium, titanium, and oxygen; and a second electrode placed on or above the piezoelectric layer.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: June 28, 2022
    Inventors: Koji Sumi, Tomokazu Kobayashi, Tomohiro Sakai, Kazuya Kitada, Koichi Morozumi, Tsutomu Asakawa
  • Patent number: 11081573
    Abstract: A semiconductor element includes a semiconductor substrate; a collector layer on the semiconductor substrate; a base layer on the collector layer; an emitter layer on the base layer; emitter wiring electrically coupled to the emitter layer; a top metal layer on the emitter wiring; a first protective film covering the emitter wiring and the top metal layer, the first protective film having a first opening that overlaps at least the collector layer; and a bump including an under-bump metal layer electrically coupled to the emitter wiring via the first opening, the under-bump metal layer being larger than the first opening in plan-view area. The first protective film has an inner edge around the first opening, and the inner edge is on the top metal layer.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: August 3, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi Kurokawa, Kazuya Kobayashi
  • Patent number: 10950548
    Abstract: A semiconductor device includes electrodes which contain Au and which are placed above conductive layers in a region adjacent to stacked insulating films and also includes base layers which are composed of compositionally modulated layers and which are placed between the electrodes and the conductive layers. The base layers include lateral end sections composed of single layers projecting from lateral end sections of the electrodes in the direction of the interlayer interface between the insulating films; sections which are located under the electrodes and of which a major compositional component is Ti or Ti and W; and projecting sections which project from under the electrodes in the direction of the interlayer interface between the insulating films and of which compositional components are compositionally modulated to Ti and O, to Ti, O, and N, or to Ti, W, O, and N.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: March 16, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuichi Sano, Atsushi Kurokawa, Kazuya Kobayashi
  • Publication number: 20210039635
    Abstract: An in-vehicle controlling apparatus, comprising an evaluation unit configured to evaluate a sense-of-security level a passenger may feel with respect to an object present in a traveling direction of a self-vehicle, and a signal generation unit configured to generate a predetermined signal based on the sense-of-security level, wherein the evaluation unit evaluates the sense-of-security level based on a time headway and a temporal variation component of the time headway.
    Type: Application
    Filed: August 3, 2020
    Publication date: February 11, 2021
    Inventors: Kazuya KOBAYASHI, Ken AMEMIYA, Soichiro UEURA
  • Patent number: 10777667
    Abstract: A semiconductor device has bipolar transistors on a substrate. There is also an insulating film on the substrate, covering the bipolar transistors. On this insulating film is emitter wiring, sticking through openings in the insulating film (first openings) to be electrically coupled to the emitter layer of the bipolar transistors. On the emitter wiring is a protective film. On the protective film is a bump, sticking through an opening in the protective film (second opening) to be electrically coupled to the emitter wiring. In plan view, the second opening is included in the area that is inside the bump and outside the first openings.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: September 15, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi Kurokawa, Koshi Himeda, Kazuya Kobayashi
  • Publication number: 20200243671
    Abstract: A semiconductor element includes a semiconductor substrate; a collector layer on the semiconductor substrate; a base layer on the collector layer; an emitter layer on the base layer; emitter wiring electrically coupled to the emitter layer; a top metal layer on the emitter wiring; a first protective film covering the emitter wiring and the top metal layer, the first protective film having a first opening that overlaps at least the collector layer; and a bump including an under-bump metal layer electrically coupled to the emitter wiring via the first opening, the under-bump metal layer being larger than the first opening in plan-view area. The first protective film has an inner edge around the first opening, and the inner edge is on the top metal layer.
    Type: Application
    Filed: January 24, 2020
    Publication date: July 30, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi KUROKAWA, Kazuya KOBAYASHI