Abstract: A semiconductor memory device enables multi-direction data access at a high speed with a simple circuit construction. The semiconductor memory device includes a plurality of word lines, a plurality of bit lines and a plurality of memory cells connected to the bit lines and word lines. A row decoder, connected to the word lines, selects one of the word lines in response to a row address signal. A selection circuit includes a plurality of column decoders and a direction decoder. Each column decoder receives a portion of a column address signal and the direction decoder selects one of three directions in response to a direction address signal. Each column decoder is selectively enabled based upon the direction address signal. Output circuitry outputs data read out from bit lines selected by the enabled column decoders. Thus, three-dimensional bit map data can be stored in two dimensions.

Abstract: The present invention relates to a manufacturing process for ring-shaped parts having high wear resistance and mechanical strength. Raw material powder containing (weight %) C at 0.4-0.9%, Ni at 1.5-4.0%, Mo 0.2-0.6%, and a remainder consisting of Fe and unavoidable impurities, is compacted and shaped, thereafter sintered and forged; obtained sintered body is hardened by heating at a temperature within a range of 800.degree.-950.degree. C., thereafter high temperature tempering is carried out for 20-60 minutes at a temperature within a range of 570.degree.-700.degree. C.; then the surface layer of the inner periphery and/or outer periphery of said sintering body is heated; then if required, low temperature tempering (temper process) is carried out at a temperature within a range of 160.degree.-220.degree. C.

Abstract: A semiconductor memory device includes: a circuit for defining a cycle in response to a clock and a write enable signal and outputting a write control signal under a specific condition; a unit for inverting the clock to an inverted clock; a circuit for generating a write signal in response to the inverted clock when the write control signal is output; and a memory cell array in which a write access of data is carried out based on the write signal. Where a latch circuit is further provided which latches the write data and transmits the write data to the memory cell array in response to the clock or inverted clock and the write signal, an input terminal and an output terminal can be made common by making a latch timing of the write data different from that of the write enable signal, or the number of input terminals can be decreased by inputting the write data in a time sharing mode. This results in a decrease in scale of the whole circuit as a device.

Abstract: A semiconductor memory device having a register and a memory cell array includes a controlling circuit for disconnecting an input/output circuit from a data bus and turning OFF a transfer gate provided between the register and data bus in a first operation mode and for connecting the input/output circuit to the data bus and turning ON the transfer gate in a second operation mode. In the first operation mode, a data read or write operation is performed between the memory cell array and an external circuit, and alternatively in the second operation mode the data read or write operation is performed between the register and the external circuit.