Abstract: A storage control apparatus includes a standard read request unit, an error correcting unit, and a high-accuracy read request unit. The standard read request unit is configured to issue a request for a read with standard accuracy to a read address in a memory. The error correcting unit is configured to perform error correction on the basis of an error correcting code and data returned by the memory in response to the read request with the standard accuracy. The high-accuracy read request unit is configured to issue, when an error incapable of being corrected by the error correction is caused, a request again for a read with higher accuracy than the standard accuracy to the read address.

Abstract: Disclosed herein is a storage controlling apparatus, including: a status acquisition section configured to acquire status including a number of times of execution of verification after writing into a memory from the memory; a history information retention section configured to retain a history of the status as history information in an associated relationship with each of predetermined regions of the memory; and a region selection section configured to select a region which satisfies a condition in accordance with the history information when a new region is to be used in the memory.

Abstract: A storage control device includes a first rewriting section, a second rewriting section, and a first retry control section. The first rewriting section performs first rewrite to rewrite other of two binary values into a memory cell in which one of the two binary values is written. The second rewriting section performs second rewrite to rewrite the one of the two binary values into the memory cell in which the other of the two binary values is written. The first retry control section causes the memory cell that has undergone the first rewrite to be subjected to the second rewrite followed by the first rewrite again if an error occurs during the first rewrite.

Abstract: There is provide a memory controller, which substitutes a substitution page for an error page in a block including a plurality of pages in a non-volatile memory and secures a substitution block to substitute a page in the secured substitution block for the error page when the substitution page is insufficient in a block to which the error page belongs, the substitution page being assigned to the block to which the error page belongs, the substitution block being different from the block to which the error page belongs.

Abstract: Provided is a storage control device including a first read processing unit configured to read data having any one value of a first value or a second value based on a first threshold value in a memory cell, the data being read as first read data, a first write processing unit configured to rewrite the memory cell to the first value when write data is the first value and the first read data is the second value, a second read processing unit configured to read second read data based on a second threshold value different from the first threshold value in the memory cell, and a second write processing unit configured to rewrite the memory cell to the second value when the write data is the second value and the second read data is the first value.

Abstract: A storage control apparatus includes: a pre-processing-execution determining block for determining whether or not either one of an erase operation and a program operation is to be executed as pre-processing in a write operation to be carried out on a predetermined data area to serve as a write-operation object; and a pre-read processing block for reading out pre-read data from the data area prior to the write operation if a result of the determination indicates that the pre-processing is to be executed. The apparatus further includes a bit operating block for carrying out: the pre-processing and one of the erase and program operations which is not the pre-processing as post-processing if a result of the determination indicates that the pre-processing is to be executed; and the post-processing without carrying out the pre-processing if a determination result indicates that the pre-processing is not to be executed.

Abstract: There is provided a storage apparatus that includes an address obtaining section, and a write processing section. The address obtaining section is configured to obtain a normal write address and an alternative write address before data writing to the normal write address, the normal write address being designated as a destination of the data writing, the alternative write address being used when the data writing is failed. The write processing section is configured to perform the data writing to the normal write address when instructed for the data writing, and perform the data writing to the alternative write address when the data writing to the normal write address is failed.

Abstract: A storage control apparatus includes: a pre-processing-execution determining block for determining whether or not either one of an erase operation and a program operation is to be executed as pre-processing in a write operation to be carried out on a predetermined data area to serve as a write-operation object; and a pre-read processing block for reading out pre-read data from the data area prior to the write operation if a result of the determination indicates that the pre-processing is to be executed. The apparatus further includes a bit operating block for carrying out: the pre-processing and one of the erase and program operations which is not the pre-processing as post-processing if a result of the determination indicates that the pre-processing is to be executed; and the post-processing without carrying out the pre-processing if a determination result indicates that the pre-processing is not to be executed.

Abstract: A storage control device is disclosed including a write block and a read block. The write block establishes a high-speed access data count. If a plurality of data are to be written to high- and low-speed access storage blocks, the write block writes as many data as the high-speed access data count from among the plurality of data to the high-speed access storage block as high-speed access data while writing the remaining data to the low-speed access storage block as low-speed access data. If the plurality of data written to the low- and high-speed access storage blocks are to be read, the read block issues a request to the high-speed access storage block to read the high-speed access data and a request to the low-speed access storage block to start reading the low-speed access data after the high-speed access data have been read.

Abstract: A storage control apparatus includes an uncorrectable error generation flag management section configured to manage an uncorrectable error generation flag in a memory configured to store a first error detection and correction code corresponding to a first data unit, and a second error detection and correction code corresponding to a second data unit including first data units, the uncorrectable error generation flag representing whether or not an uncorrectable error with the first code has occurred, the uncorrectable error generation flag being managed for each second data unit, a controller configured to prohibit access to the second data unit representing that the uncorrectable error has occurred when a command for the access with data change is issued, and a correction section configured to use the second code to correct the second data unit when the second data unit representing that the uncorrectable error has occurred is restored.

Abstract: A polymerizable composition is disclosed wherein the polymerizable composition includes a first component selected from the group composed of compounds produced by an ester exchange reaction between a hydrogenated polyolefin polyol and an acrylic acid ester, compounds produced by an ester exchange reaction between a hydrogenated polyolefin polyol and a methacrylic acid ester, compounds produced by a dehydration condensation reaction between a hydrogenated polyolefin polyol and an acrylic acid, and compounds produced by a dehydration condensation reaction between a hydrogenated polyolefin polyol and a methacrylic acid, a second component selected from the group composed of compounds containing a hydrocarbon group with a carbon number more than or equal to 6 and an acryloyl group and compounds containing a hydrocarbon group with a carbon number more than or equal to 6 and a methacryloyl group, and a third component selected from the group composed of photopolymerization initiators.

Abstract: Provided is a storage control device including: a detection unit which detects a first timing for performing a first rewriting process of performing only a first operation from among the first operation and a second operation, in a memory cell array in which each bit transitions to a first storage state by the first operation and transitions to a second storage state by the second operation; and a request unit which makes a request for the first rewriting process with respect to the memory cell array, when the first timing is detected.

Abstract: In relation to a polymerizable composition for forming a transparent optical resin layer to be interposed between an image display section of an image display device and a light-transmissive protective section thereof, the present invention provides a polymerizable composition that does not give rise to display defects caused by the deformation of the image display section, enables high-luminance, high-contrast image displaying, has excellent heat resistance, and also has a low dielectric constant. This polymerizable composition comprises: (1) a urethane (meth)acrylate obtained by reacting a hydrogenated polyolefin polyol and a compound having an isocyanato group and a (meth)acryloyl group; (2) a (meth)acryloyl-group-containing compound having a hydrocarbon group with a carbon number of 6 or greater; and (3) a photopolymerization initiator.

Abstract: A storage controller includes an error correcting code managing portion, an address managing portion and an error correcting portion. The error correcting code managing portion manages a correspondence relationship between predetermined plural pieces of unit data, and a second error code corresponding to the plural pieces of unit data every entry when plural pieces of unit data and a second error correcting code are stored in a storage portion. The address managing portion manages a correspondence relationship between logical addresses and the entries in the error correcting code managing portion. The error correcting portion acquires the entry in the error correction managing portion corresponding to the logical address as an object of read from the address managing portion, and carries out error correction based on the plural pieces of unit data managed in the entry concerned, and the second error correcting code.

Abstract: Disclosed herein is a nonvolatile memory including: a nonvolatile memory cell device including at least a nonvolatile memory cell array accessible in units of a word and further accessible at least with a fixed latency in a first access mode and with a variable latency in a second access mode; a first access path used in the first access mode; a second access path used in the second access mode; a first ECC processing part configured to be connected to the first access path and to perform error detection and correction using an ECC on the data output from the nonvolatile memory cell array in the first access mode; and a second ECC processing part configured to be connected to the second access path and to perform error detection and correction using the ECC on the data output from the nonvolatile memory cell array in the second access mode.

Abstract: Provided is a storage control device including a history information holding unit configured to hold history information in a predetermined data area of a memory cell holding either a first value or a second value for each bit, the history information indicating which mode of a first mode or a second mode is employed upon a previous write operation, the first mode setting all bits to the first value and then setting any bit to the second value, the second mode setting all bits to the second value and then setting any bit to the first value, and a bitwise operation unit configured to perform a write operation in the second mode if the history information indicates the first mode and to perform a write operation in the first mode if the history information indicates the second mode.

Abstract: A storage control device includes: a partial unit buffer configured to hold at least one data assigned to a partial unit, in which the partial unit is one of a plurality of partial units that are each a division of a write unit for a memory; and a request generation section configured to generate, upon indication of a busy state in the memory for any of the partial units, a write request for the write unit of the memory when the holding of the data assigned to that partial unit is possible in the partial unit buffer.

Abstract: A memory system includes: a first non-volatile memory used for storing data to be accessed in block units; a second non-volatile memory used for storing data to be accessed in word units in random accesses to the second non-volatile memory; and a control section configured to control operations of the first and second non-volatile memories, wherein error correction codes to be applied to data stored in the second non-volatile memory are held in the first non-volatile memory.

Abstract: A storage controller includes: an error information management section configured to manage information in a plurality of addresses of a memory; and a refresh object determination section configured to determine a refresh object address in the memory based on the error information.

Abstract: An error detection and correction unit includes: a first-code error detection section configured to detect whether or not each of a plurality of first code words in a second code word has an error, the second code word generated by encoding the plurality of first code words in chains and being a code word containing a plurality of partial data; and a second-code error correction section configured to correct the error in one partial data containing the first code word in which the error is detected of the plurality of partial data in the second code word, based on adjacent partial data adjacent to the one partial data.