Patents by Inventor Kenichi Nakanishi

Kenichi Nakanishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060059297
    Abstract: Memory control apparatus, memory control method, and program are provided. The present invention provides a preparatory process for determining whether or not a data-updating process to update data of a flash memory or a data-writing process to write new data into the memory has been completed normally. A data-updating process to update data stored in a specific block is carried out as a process including alternate-block processing to replace the specific block with another block referred to as an alternate block. In the current data-updating process, the alternate block is examined to determine whether or not data has been erased from the alternate block. If data has been erased from the alternate block, the preceding data-updating or data-writing process is determined to be normal. By virtue of a property exhibited by the contents of the reserved-block address, the reserved-block address needs to be saved in the flash memory only once during a data-updating or data-writing process.
    Type: Application
    Filed: September 6, 2005
    Publication date: March 16, 2006
    Inventors: Kenichi Nakanishi, Nobuhiro Kaneko
  • Publication number: 20060047889
    Abstract: A memory device and controlling method for nonvolatile memory are provided. The memory device and the controlling method for a nonvolatile memory are provided by which, where a file management system wherein there is a tendency that lower logic addresses are used frequently like the MS-DOS is adopted, physical blocks of a flash memory are used in an averaged fashion and the life of the flash memory can be elongated thereby.
    Type: Application
    Filed: August 19, 2005
    Publication date: March 2, 2006
    Inventors: Junko Sasaki, Kenichi Nakanishi, Nobuhiro Kaneko
  • Patent number: 6965963
    Abstract: 512 clusters included in one segment are distributed into 128 clusters included in each of four storages. A logical/physical address conversion table is formed every segment. Therefore, unless the segment is changed, the logical/physical address conversion table to be referred to or updated does not change, so that a deterioration of the reading performance due to an access to the table or an updating of the table can be prevented. Data can be simultaneously written into continuous logic cluster addresses, for example, 0x0004 to 0x0007, and the high speed writing operation can be realized.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: November 15, 2005
    Assignee: Sony Corporation
    Inventors: Kenichi Nakanishi, Shigeo Araki
  • Publication number: 20050182892
    Abstract: The invention provides a data storage device and a method of updating management information, capable of dealing with management information in a highly reliable manner so that information is not easily lost when an error occurs. File management information such as a FAT serving as address management information in a flash memory is stored in a management information area of the memory, a pair of blocks is assigned as blocks for use to store data of the FAT, and writing of updated FAT information is performed by alternately using the two blocks of the block pair such that previous FAT information is retained in one of the two blocks of the block pair, and updated FAT information is written in the other block of the block pair, whereby, even when an error occurs in the middle of the process of writing the updated management information, a process using the retained previous FAT information is possible.
    Type: Application
    Filed: March 5, 2004
    Publication date: August 18, 2005
    Inventors: Kenichi Nakanishi, Junko Sasaki, Nobuhiro Kaneko, Osamu Nagata, Hideaki Okubo
  • Publication number: 20050174857
    Abstract: A nonvolatile-memory controlling method is disclosed which continuously accesses a plurality of memory banks structured so as to have each memory bank accessible independently. The method comprises the steps of: in a busy cycle of one of the plurality of memory banks being accessed, issuing access information to a second memory bank for access thereto; bringing the second memory bank into a selected state while the access information is being issued to the second memory bank using a selection signal for controlling a selected state and an unselected state for any one of the plurality of memory banks; bringing the memory bank in the busy cycle into an unselected state while the access information is being issued; and accessing the plurality of memory banks continuously based on the access information issued to the second memory bank in the busy cycle of one of the memory banks being accessed and in keeping with the selection signal for controlling the second memory bank.
    Type: Application
    Filed: February 2, 2005
    Publication date: August 11, 2005
    Applicant: Sony Corporation
    Inventors: Takahiro Fukushige, Kenichi Satori, Kenichi Nakanishi, Hideaki Bando, Junko Sasaki, Kunihiko Miura, Toshinori Nakamura, Kensuke Hatsukawa
  • Publication number: 20050086433
    Abstract: This invention provides a memory card (1) that is to be used as a storage medium in a host apparatus that can record and reproduce data. The memory card has a first memory (12-1), a second memory (12-2), a first switch (13) for changing over one memory to the other, and a second switch (14) for connecting and disconnecting an insertion/removal detecting terminal INS. The first and second switches work as a slide switch (6) provided on the housing is operated. The first switch has a contact for selecting the first memory, a contact for selecting the second memory, and a contact located between these two contacts, for selecting neither memory. The second switch connects the terminal INS to the ground while the first switch remains connected to the contact for selecting the first memory or the contact for selecting the second memory. The second switch opens the terminal INS while the first switch remains connected to the contact for selecting neither memory.
    Type: Application
    Filed: October 7, 2003
    Publication date: April 21, 2005
    Inventors: Takumi Okaue, Shigeo Araki, Junko Sasaki, Kenichi Nakanishi
  • Publication number: 20040243779
    Abstract: A device and method is provided for maintaining, upon unlocking of a memory, the lock status of the memory prior to the memory being unlocked and recreating the lock status when power is turned on again. An information storage device, such as a memory card, performs unlocking of a memory in response to a command input from an information processing apparatus and stores lock status data prior to the memory being unlocked in a non-volatile memory (NVM). When the information storage device is turned off and then on, the information storage device recreates a lock status of the memory on the basis of the lock status data stored in the storage means and performs memory access control based on the recreated lock status.
    Type: Application
    Filed: June 28, 2004
    Publication date: December 2, 2004
    Inventors: Takumi Okaue, Kenichi Nakanishi, Jun Tashiro, Hideaki Okubo
  • Publication number: 20040236918
    Abstract: A device and method is provided for performing access control on a memory by locking/unlocking the memory on the basis of verification of a key set output from an access request source. An information storage device, such as a memory card, receives a locking request command to lock a memory or an unlocking request command to unlock the memory from an information processing apparatus, such as a PC. Upon performing processing in response to the received command, the information storage device verifies whether the information processing apparatus has a valid key set consisting of an ID and a lock key (LK) by applying a lock master key (LMK) based on the relationship LK=H(LMK, ID). The information storage device performs processing based on the command provided that the verification succeeds.
    Type: Application
    Filed: June 14, 2004
    Publication date: November 25, 2004
    Inventors: Takumi Okaue, Kenichi Nakanishi, Jun Tashiro, Hideaki Okubo
  • Publication number: 20040236919
    Abstract: A device and method is provided for locking a memory provided that it is determined that data stored in the memory is read from a predetermined data region. An information storage device, such as a memory card, determines, when data is read from a memory in response to a request from a host device connected to the information storage device, whether a data region from which the data is read is a locking-associated data region on the basis of, for example, a cluster logical number. The memory is locked provided that it is determined that the locking-associated data region is read. According to the present structure, data is prevented from being read multiple times from an information storage device, such as a memory card, thereby implementing so-called read-once access control.
    Type: Application
    Filed: June 14, 2004
    Publication date: November 25, 2004
    Inventors: Takumi Okaue, Kenichi Nakanishi, Jun Tashiro, Hideaki Okubo
  • Publication number: 20040215910
    Abstract: A device and method is provided for commonly and securely allowing, as access control on a memory card, a plurality of information processing apparatuses to lock/unlock the memory. On the basis of a lock command input from an information processing apparatus serving as a host, such as a PC, an information storage device, such as a memory card, determines whether (a) a standard lock key set serving as a key set prohibiting output or (b) an export lock key set serving as a key set permitting output is detected and stores corresponding key set information. Only when the export lock key set is detected, output is permitted provided that predetermined verification succeeds.
    Type: Application
    Filed: February 6, 2004
    Publication date: October 28, 2004
    Inventors: Takumni Okaue, Kenichi Nakanishi, Jun Tashiro, Hideaki Okubo
  • Patent number: 6681269
    Abstract: A data processing apparatus and an external storage apparatus arranged to transmit data by using serial signals and capable of reducing the number of signal lines for use to transmit serial data. A CLK line, a control line and a DT line are arranged between a data processing apparatus and a memory card. The DT line is a line through which data and commands formed into serial signals are bidirectionally transmitted. A synchronizing signal is transmitted to the CLK line. A control signal is supplied from the data processing apparatus to the memory card through the control line. In a period of time in which the signal level of the control signal is a high level, data or a command is transmitted to the DT line. In a period of time in which the signal level of the control signal is a low level, a status signal is transmitted to the DT line from the memory card.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: January 20, 2004
    Assignee: Sony Corporation
    Inventors: Mitsuhiro Hirabayashi, Kenichi Nakanishi
  • Publication number: 20030074497
    Abstract: A data processing apparatus and an external storage apparatus arranged to transmit data by using serial signals and capable of reducing the number of signal lines for use to transmit serial data. A CLK line, a control line and a DT line are arranged between a data processing apparatus and a memory card. The DT line is a line through which data and commands formed into serial signals are bidirectionally transmitted. A synchronizing signal is transmitted to the CLK line. A control signal is supplied from the data processing apparatus to the memory card through the control line. In a period of time in which the signal level of the control signal is a high level, data or a command is transmitted to the DT line. In a period of time in which the signal level of the control signal is a low level, a status signal is transmitted to the DT line from the memory card.
    Type: Application
    Filed: November 22, 2002
    Publication date: April 17, 2003
    Applicant: SONY CORPORATION
    Inventors: Mitsuhiro Hirabayashi, Kenichi Nakanishi
  • Patent number: 6525952
    Abstract: Data 30 is recorded into storages 0 to 3 in parallel. Writing sectors are selected from a plurality of clusters so that the sectors are continuously arranged in each cluster, and the data is simultaneously written into the selected sectors. In the case where the sectors numbered in the original order are written into the storages 0 to 3 in parallel, the data of No. 0 is recorded into the head sector in the cluster of the storage 0, the data of No. 16 is recorded into the head sector in the cluster of the storage 1, the data of No. 32 is recorded into the head sector in the cluster of the storage 2, and the data of No. 48 is recorded into the head sector in the cluster of the storage 3, respectively. Thus, the data is arranged in the original order into the cluster constructed in the same storage. When the data is written into a plurality of storages in parallel, the compatibility of the file format of the written data is held.
    Type: Grant
    Filed: April 8, 2002
    Date of Patent: February 25, 2003
    Assignee: Sony Corporation
    Inventors: Shigeo Araki, Kenichi Nakanishi
  • Publication number: 20030014582
    Abstract: The present invention provides an apparatus for recording data, including a storage unit (4) for reading out management information stored in the flash memory (2) to store read out management information, an updating unit (7) for updating management information stored in the storage unit (4), a management information writing unit (3) for writing management information updated by the updating unit (7) to the page being a unit in writing data to the flash memory (2), and a control unit (7) for controlling the management information writing unit (3) so that, when the management information writing unit (3) writes updated management information to a page of the flash memory (2), a block which is different from a block including a page in which management information just before updating is written is selected, and updated management information is written to a vacant page of thus selected block.
    Type: Application
    Filed: August 22, 2002
    Publication date: January 16, 2003
    Inventor: Kenichi Nakanishi
  • Patent number: 6496879
    Abstract: A data processing apparatus and an external storage apparatus arranged to transmit data by using serial signals and capable of reducing the number of signal lines for use to transmit serial data. A CLK line, a control line and a DT line are arranged between a data processing apparatus and a memory card. The DT line is a line through which data and commands formed into serial signals are bidirectionally transmitted. A synchronizing signal is transmitted to the CLK line. A control signal is supplied from the data processing apparatus to the memory card through the control line. In a period of time in which the signal level of the control signal is a high level, data or a command is transmitted to the DT line. In a period of time in which the signal level of the control signal is a low level, a status signal is transmitted to the DT line from the memory card.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: December 17, 2002
    Assignee: Sony Corporation
    Inventors: Mitsuhiro Hirabayashi, Kenichi Nakanishi
  • Publication number: 20020110014
    Abstract: Data 30 is recorded into storages 0 to 3 in parallel. Writing sectors are selected from a plurality of clusters so that the sectors are continuously arranged in each cluster, and the data is simultaneously written into the selected sectors. In the case where the sectors numbered in the original order are written into the storages 0 to 3 in parallel, the data of No. 0 is recorded into the head sector in the cluster of the storage 0, the data of No. 16 is recorded into the head sector in the cluster of the storage 1, the data of No. 32 is recorded into the head sector in the cluster of the storage 2, and the data of No. 48 is recorded into the head sector in the cluster of the storage 3, respectively. Thus, the data is arranged in the original order into the cluster constructed in the same storage. When the data is written into a plurality of storages in parallel, the compatibility of the file format of the written data is held.
    Type: Application
    Filed: April 8, 2002
    Publication date: August 15, 2002
    Applicant: SONY CORPORATION
    Inventors: Shigeo Araki, Kenichi Nakanishi
  • Publication number: 20020099877
    Abstract: A data processing apparatus and an external storage apparatus arranged to transmit data by using serial signals and capable of reducing the number of signal lines for use to transmit serial data. A CLK line, a control line and a DT line are arranged between a data processing apparatus and a memory card. The DT line is a line through which data and commands formed into serial signals are bidirectionally transmitted. A synchronizing signal is transmitted to the CLK line. A control signal is supplied from the data processing apparatus to the memory card through the control line. In a period of time in which the signal level of the control signal is a high level, data or a command is transmitted to the DT line. In a period of time in which the signal level of the control signal is a low level, a status signal is transmitted to the DT line from the memory card.
    Type: Application
    Filed: March 25, 2002
    Publication date: July 25, 2002
    Applicant: SONY CORPORATION
    Inventors: Mitsuhiro Hirabayashi, Kenichi Nakanishi
  • Patent number: 6412023
    Abstract: A data processing apparatus and an external storage apparatus arranged to transmit data by using serial signals and capable of reducing the number of signal lines for use to transmit serial data. A CLK line, a control line and a DT line are arranged between a data processing apparatus and a memory card. The DT line is a line through which data and commands formed into serial signals are bidirectionally transmitted. A synchronizing signal is transmitted to the CLK line. A control signal is supplied from the data processing apparatus to the memory card through the control line. In a period of time in which the signal level of the control signal is a high level, data or a command is transmitted to the DT line. In a period of time in which the signal level of the control signal is a low level, a status signal is transmitted to the DT line from the memory card.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: June 25, 2002
    Assignee: Sony Corporation
    Inventors: Mitsuhiro Hirabayashi, Kenichi Nakanishi
  • Patent number: 6388908
    Abstract: Data 30 is recorded into storages 0 to 3 in parallel. Writing sectors are selected from a plurality of clusters so that the sectors are continuously arranged in each cluster, and the data is simultaneously written into the selected sectors. In the case where the sectors numbered in the original order are written into the storages 0 to 3 in parallel, the data of No. 0 is recorded into the head sector in the cluster of the storage 0, the data of No. 16 is recorded into the head sector in the cluster of the storage 1, the data of No. 32 is recorded into the head sector in the cluster of the storage 2, and the data of No. 48 is recorded into the head sector in the cluster of the storage 3, respectively. Thus, the data is arranged in the original order into the cluster constructed in the same storage. When the data is written into a plurality of storages in parallel, the compatibility of the file format of the written data is held.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: May 14, 2002
    Assignee: Sony Corporation
    Inventors: Shigeo Araki, Kenichi Nakanishi
  • Patent number: 6253259
    Abstract: A data processing apparatus and an external storage apparatus arranged to transmit data by using serial signals and capable of reducing the number of signal lines for use to transmit serial data. A CLK line, a control line and a DT line are arranged between a data processing apparatus and a memory card. The DT line is a line through which data and commands formed into serial signals are bidirectionally transmitted. A synchronizing signal is transmitted to the CLK line. A control signal is supplied from the data processing apparatus to the memory card through the control line. In a period of time in which the signal level of the control signal is a high level, data or a command is transmitted to the DT line. In a period of time in which the signal level of the control signal is a low level, a status signal is transmitted to the DT line from the memory card.
    Type: Grant
    Filed: May 21, 1998
    Date of Patent: June 26, 2001
    Assignee: Sony Corporation
    Inventors: Mitsuhiro Hirabayashi, Kenichi Nakanishi