Abstract: A memory system includes: a first non-volatile memory used for storing data to be accessed in block units; a second non-volatile memory used for storing data to be accessed in word units in random accesses to the second non-volatile memory; and a control section configured to control operations of the first and second non-volatile memories, wherein error correction codes to be applied to data stored in the second non-volatile memory are held in the first non-volatile memory.

Abstract: A storage control apparatus includes a standard read request unit, an error correcting unit, and a high-accuracy read request unit. The standard read request unit is configured to issue a request for a read with standard accuracy to a read address in a memory. The error correcting unit is configured to perform error correction on the basis of an error correcting code and data returned by the memory in response to the read request with the standard accuracy. The high-accuracy read request unit is configured to issue, when an error incapable of being corrected by the error correction is caused, a request again for a read with higher accuracy than the standard accuracy to the read address.

Abstract: Disclosed herein is a nonvolatile memory, including: a memory area including a data area configured to retain data and an error correction code area configured to retain an error correction code known as ECC; and a control unit configured to control access to the memory area. The control unit includes an error detection and correction function configured to detect an error in the data read from the data area and to correct the detected error, at least one save area configured such that if data at a designated address and ECC corresponding thereto are read from the memory area and if an error is detected, then the save area retaining the address and correct data corresponding thereto, and a validity presentation block configured to indicate whether or not the address and the correct data retained in the save area are valid.

Abstract: Provided is a memory control device, including a write control unit that sequentially designates a memory block, a write processing unit that writes write data in the designated memory block, a verifying unit that reads read data from the memory block and verifies whether or not the read data matches the write data for each of a plurality of memory cells, a retry inhibiting unit that inhibits a retry process from being performed in a memory cell in which the read data matches the write data among the plurality of memory cells, and a retry control unit that designates at least some memory blocks among the plurality of memory blocks and simultaneously executes the retry process when the read data does not match the write data in any one of the plurality of memory cells in which all the write data is written.

Abstract: There is provided a memory control device, including a request determining unit that determines a type of a request, and a control unit that writes read data read from a memory cell array in the memory cell array in units of predetermined pages of the memory cell array when the request is a refresh request, and divides the page of write data into units of groups and writes the page of the write data in the memory cell array over twice or more when the request is a write request.

Abstract: There is provided a storage control apparatus including a memory state acquisition unit acquiring a storage state of a memory associated with a write target, and an operation instruction generation unit generating an operation instruction of at least 2 bits per cell of the memory associated with the write target, from the acquired storage state and write data.

Abstract: There is provided a storage control device including a read processing unit that reads data and inversion state information indicating whether the data is in an inverted state or a non-inverted state from a specific region of a memory cell array that stores the data and the inversion state information with first intensity in association, and a write processing unit that writes data obtained by inverting the data and a state obtained by changing a state indicated by the inversion state information to an opposite state in the specific region with second intensity that is different from the first intensity.

Abstract: There is provided a memory control apparatus including: a pre-read processing section reading pre-read data from a data area to be written to before a write process in a predetermined data area of a memory cell array; a conversion determination section which, upon selectively allowing the pre-read data to transition to either a first conversion candidate or a second conversion candidate of the write data to be written in the write process, generates a determination result for selecting either of the candidates based on the larger of two values of which one is the number of bits transitioning from the first value to the second value and of which the other is the number of bits transitioning from the second value to the first value; and a conversion control section selecting either of the candidates in accordance with the determination result.

Abstract: A storage controlling apparatus includes a command decoder and command processing section. The command decoder decides whether or not a plurality of access object addresses of different commands included in a command string correspond to words different from each other in a same one of blocks of a memory cell array which have a common plate. The command processing section collectively and successively executes, when it is decided that the access object addresses of the commands correspond to the words different from each other in the same block of the memory cell array, those of operations in processing of the commands in which an equal voltage is applied as a drive voltage between the plate and a bit line.

Abstract: A storage control device includes a first rewriting section, a second rewriting section, and a first retry control section. The first rewriting section performs first rewrite to rewrite other of two binary values into a memory cell in which one of the two binary values is written. The second rewriting section performs second rewrite to rewrite the one of the two binary values into the memory cell in which the other of the two binary values is written. The first retry control section causes the memory cell that has undergone the first rewrite to be subjected to the second rewrite followed by the first rewrite again if an error occurs during the first rewrite.

Abstract: Disclosed herein is a storage controlling apparatus, including: a status acquisition section configured to acquire status including a number of times of execution of verification after writing into a memory from the memory; a history information retention section configured to retain a history of the status as history information in an associated relationship with each of predetermined regions of the memory; and a region selection section configured to select a region which satisfies a condition in accordance with the history information when a new region is to be used in the memory.

Abstract: Disclosed herein is a storage controlling apparatus including: a decision portion configured to decide whether or not a bit number of a specific value from between binary values is greater than a reference value in at least part of input data to a memory cell, which executes rewriting to one of the binary values and rewriting to the other one of the binary values in order in a writing process, to generate decision data indicative of a result of the decision; and a write side outputting portion configured to output, when it is decided that the bit number is greater than the reference value, the input data at least part of which is inverted as write data to the memory cell together with the decision data.

Abstract: Disclosed herein is a storage control apparatus including: a command processing section configured to receive a command requesting accesses to a plurality of access units by specifying an address in a memory space including a plurality of banks; and an address generating section configured to generate an address of an access unit serving as an object of the accesses in a bank selected from the banks as a bank determined in advance for the specified address.

Abstract: A storage control apparatus includes: a pre-processing-execution determining block for determining whether or not either one of an erase operation and a program operation is to be executed as pre-processing in a write operation to be carried out on a predetermined data area to serve as a write-operation object; and a pre-read processing block for reading out pre-read data from the data area prior to the write operation if a result of the determination indicates that the pre-processing is to be executed. The apparatus further includes a bit operating block for carrying out: the pre-processing and one of the erase and program operations which is not the pre-processing as post-processing if a result of the determination indicates that the pre-processing is to be executed; and the post-processing without carrying out the pre-processing if a determination result indicates that the pre-processing is not to be executed.

Abstract: A memory control method is disclosed which includes: a storing step of storing a logical to physical conversion table retaining relations of correspondence between addresses of logical blocks in a user data area on the one hand, and addresses of physical blocks assigned to the logical blocks on the other hand, along with addresses of physical blocks in a cache area, the physical block addresses corresponding to the physical block addresses in the logical to physical conversion table; a first writing step of writing, to a deleted new cache block in the cache area, data in excess of a designated logical boundary which defines a logical space size in units of a plurality of sectors within a user data block of the user data area; and a second writing step of writing the data starting from the beginning of the new cache block upon data write in the first writing step to the new cache block, regardless of the logical address space of the new cache block.

Abstract: An information storage apparatus transmits or receives information to or from another information processing apparatus in one of a plurality of data transfer modes. The information storage apparatus includes first storage means for storing the information; information transmission/reception control means for controlling transmission or reception of the information between the first storage means and second storage means contained in the other information processing apparatus; command analysis means for analyzing a command supplied from the other information processing apparatus to determine which of the plurality of data transfer modes should be applied; and configuration means for configuring the information transmission/reception control means based on a result of determination of the data transfer mode by the command analysis means.

Abstract: A memory apparatus includes a memory having a main memory area and a replacement area, and a memory controller having a function of issuing instructions corresponding to commands to carry out transmission and reception of data and reading of status information of the memory.

Abstract: Disclosed herein is a nonvolatile memory apparatus including, a nonvolatile memory section, a standard error correction code processing section, an extended error correction code processing section, and a control section.

Abstract: A nonvolatile random access memory includes: a nonvolatile storage area that is randomly accessible and includes a data area to store data and an error-correcting-code area to store an error correcting code, the data area including at least one data area to which a data area unit size is assigned, the error-correcting-code area including at least one error-correcting-code area to which an error-correcting-code-area unit size is assigned; and a nonvolatile storage area controller to set a data size used when the at least one data area is accessed, as the data area unit size. The nonvolatile storage area controller manages the data area and the error-correcting-code area based on the set data area unit size and assigns the at least one error-correcting-code area with the error-correcting-code-area unit size to the at least one data area with the data area unit size based on the data area unit size.

Abstract: A device and method is provided for commonly and securely allowing, as access control on a memory card, a plurality of information processing apparatuses to lock/unlock the memory. On the basis of a lock command input from an information processing apparatus serving as a host, such as a PC, an information storage device, such as a memory card, determines whether (a) a standard lock key set serving as a key set prohibiting output or (b) an export lock key set serving as a key set permitting output is detected and stores corresponding key set information. Only when the export lock key set is detected, output is permitted provided that predetermined verification succeeds.