Patents by Inventor Kenichi Okazaki

Kenichi Okazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11871600
    Abstract: A display device with high display quality is provided. The display device includes a first lower electrode, a first EL layer over the first lower electrode, a second lower electrode, a second EL layer over the second lower electrode, an upper electrode over the first EL layer and the second EL layer, a first region not provided with the first lower electrode below the first EL layer, and a second region not provided with the second lower electrode below the second EL layer. In the first region, the upper electrode is positioned not to be in contact with the first lower electrode. In the second region, the upper electrode is positioned not to be in contact with the second lower electrode.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: January 9, 2024
    Inventors: Kenichi Okazaki, Shingo Eguchi, Hiroki Adachi
  • Patent number: 11862454
    Abstract: A change in electrical characteristics in a semiconductor device including an oxide semiconductor film is inhibited, and the reliability is improved. The semiconductor device includes a gate electrode, a first insulating film over the gate electrode, an oxide semiconductor film over the first insulating film, a source electrode electrically connected to the oxide semiconductor film, a drain electrode electrically connected to the oxide semiconductor film, a second insulating film over the oxide semiconductor film, the source electrode, and the drain electrode, a first metal oxide film over the second insulating film, and a second metal oxide film over the first metal oxide film. The first metal oxide film contains at least one metal element that is the same as a metal element contained in the oxide semiconductor film. The second metal oxide film includes a region where the second metal oxide film and the first metal oxide film are mixed.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: January 2, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kenichi Okazaki, Masami Jintyou
  • Publication number: 20230420614
    Abstract: A high-resolution, high-definition, or large display apparatus is provided. A metal mask is placed over an EL layer and film deposition is performed with the metal mask, whereby an island-shaped counter electrode is formed. Then, the EL layer is processed using the counter electrode as a hard mask. Alternatively, after an EL layer and a counter electrode are formed over an entire surface, processing using a metal mask is performed. An insulating layer that electrically insulates adjacent pixel electrodes from each other is positioned between adjacent light-emitting devices. A resist mask is formed over the insulating layer. A plurality of EL layers and a plurality of counter electrodes overlapping each other over the insulating layer are partly removed using the resist mask, whereby part of the insulating layer is exposed. Thus, the adjacent light-emitting devices are electrically insulated from each other over the insulating layer.
    Type: Application
    Filed: November 25, 2021
    Publication date: December 28, 2023
    Inventors: Shunpei YAMAZAKI, Shingo EGUCHI, Tomoya AOYAMA, Daiki NAKAMURA, Kenichi OKAZAKI
  • Publication number: 20230420569
    Abstract: The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.
    Type: Application
    Filed: September 8, 2023
    Publication date: December 28, 2023
    Inventors: Shunpei YAMAZAKI, Masahiro WATANABE, Mitsuo MASHIYAMA, Kenichi OKAZAKI, Motoki NAKASHIMA, Hideyuki KISHIDA
  • Publication number: 20230420568
    Abstract: The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.
    Type: Application
    Filed: September 8, 2023
    Publication date: December 28, 2023
    Inventors: Shunpei YAMAZAKI, Masahiro WATANABE, Mitsuo MASHIYAMA, Kenichi OKAZAKI, Motoki NAKASHIMA, Hideyuki KISHIDA
  • Publication number: 20230422592
    Abstract: Manufacturing equipment of a light-emitting device with which steps from formation to sealing of a light-emitting element can be successively performed is provided. The manufacturing equipment includes a vacuum controlled cluster and an atmosphere controlled cluster and has a function of forming the light-emitting device by forming, over a substrate provided with a first electrode, an island-shaped organic compound over the first electrode, a second electrode over the organic compound, and a protective film over the second electrode through a plurality of film formation steps in the vacuum cluster, a lithography step in the atmosphere controlled cluster, and an etching step in the vacuum cluster.
    Type: Application
    Filed: November 25, 2021
    Publication date: December 28, 2023
    Inventors: Shingo EGUCHI, Hiroki ADACHI, Kenichi OKAZAKI, Naoto KUSUMOTO, Kensuke YOSHIZUMI, Shunpei YAMAZAKI
  • Publication number: 20230420522
    Abstract: A metal oxide film includes indium, M, (M is Al, Ga, Y, or Sn), and zinc and includes a region where a peak having a diffraction intensity derived from a crystal structure is observed by X-ray diffraction in the direction perpendicular to the film surface. Moreover, a plurality of crystal parts is observed in a transmission electron microscope image in the direction perpendicular to the film surface. The proportion of a region other than the crystal parts is higher than or equal to 20% and lower than or equal to 60%.
    Type: Application
    Filed: September 8, 2023
    Publication date: December 28, 2023
    Applicant: Semiconductor Energy Laboratory Co., Lid.
    Inventors: Yasuharu Hosaka, Toshimitsu OBONAI, Yukinori SHIMA, Masami JINTYOU, Daisuke KUROSAKI, Takashi HAMOCHI, Junichi KOEZUKA, Kenichi OKAZAKI, Shunpei YAMAZAKI
  • Patent number: 11856836
    Abstract: A high-yield fabricating method of a semiconductor device including a peeling step is provided. A peeling method includes a step of stacking and forming a first material layer and a second material layer over a substrate and a step of separating the first material layer and the second material layer from each other. The second material layer is formed over the substrate with the first material layer therebetween. The first material layer includes a first compound layer in contact with the second material layer and a second compound layer positioned closer to the substrate side than the first compound layer is. The first compound layer has the highest oxygen content among the layers included in the first material layer. The second compound layer has the highest nitrogen content among the layers included in the first material layer. The second material layer includes a resin.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: December 26, 2023
    Inventors: Seiji Yasumoto, Kayo Kumakura, Yuka Sato, Satoru Idojiri, Hiroki Adachi, Kenichi Okazaki
  • Patent number: 11852937
    Abstract: The manufacturing yield of a display device is improved. The resistance of a display device to ESD is increased. The display device includes a substrate, a display portion, a connection terminal, a first wiring, and a second wiring. The first wiring is electrically connected to the connection terminal and includes a portion positioned between the connection terminal and the display portion. The second wiring is electrically connected to the connection terminal, is positioned between the connection terminal and an end portion of the substrate, and includes a portion in which a side surface is exposed at an end portion of the substrate. The display portion includes a transistor. The transistor includes a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer and the second wiring include a metal oxide.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: December 26, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kenichi Okazaki, Yukinori Shima, Daisuke Kurosaki, Masataka Nakada
  • Publication number: 20230413630
    Abstract: Parasitic capacitance of a wiring in a display device is decreased. A display device having both a high definition and a high frame frequency is provided. A high-resolution display device is provided. A semiconductor device used in the display device includes a first resin layer between a first wiring and a transistor, a first insulating layer between the first resin layer and the transistor, a second resin layer between the transistor and a second wiring, and a second insulating layer between the second resin layer and the transistor. The first insulating layer and the second insulating layer include an inorganic insulating film containing nitrogen. Furthermore, the first resin layer and the second resin layer have lower permittivities than the first insulating layer and the second insulating layer, respectively, and are greater than or equal to five times and less than or equal to 100 times as thick as the first insulating layer and the second insulating layer, respectively.
    Type: Application
    Filed: November 2, 2021
    Publication date: December 21, 2023
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Kenichi OKAZAKI
  • Publication number: 20230403920
    Abstract: A novel display panel having good functionality is provided. Provided are a display panel and a manufacturing method of the display panel, including forming an insulator including at least a first opening portion and a second opening portion over a substrate, forming a first material layer including an organic compound of a first light-emitting element in the first opening portion and a second material layer including an organic compound of a second light-emitting element in the second opening portion by a wet process, forming a first resist mask and a second resist mask respectively over the first material layer and the second material layer selectively, and forming a third material layer by processing the first material layer with the first resist mask, and forming a fourth material layer by processing the second material layer with the second resist mask. As the organic compounds of the light-emitting elements, a hole-transport material, a light-emitting material, and the like can be used.
    Type: Application
    Filed: November 22, 2021
    Publication date: December 14, 2023
    Inventors: Shunpei YAMAZAKI, Shingo EGUCHI, Kenichi OKAZAKI
  • Publication number: 20230403881
    Abstract: A novel display panel that is highly convenient, useful, or reliable is provided. The display panel includes a first light-emitting device, a second light-emitting device, and a partition, the first light-emitting device includes a first electrode, a second electrode, and a first layer, and the first layer includes a region interposed between the second electrode and the first electrode. The first layer contains a first material having a hole-transport property and a first substance having an acceptor property, and has a predetermined electrical resistivity. The second light-emitting device includes a third electrode, a fourth electrode, and a second layer, and the second layer includes a region interposed between the fourth electrode and the third electrode. The second layer contains the first material having the hole-transport property and the first substance having the acceptor property, and the second layer includes a first gap between the second layer and the first layer.
    Type: Application
    Filed: November 5, 2021
    Publication date: December 14, 2023
    Inventors: Shunpei YAMAZAKI, Shingo EGUCHI, Satoshi SEO, Kenichi OKAZAKI
  • Patent number: 11841595
    Abstract: To suppress a variation in characteristics of a transistor due to a released gas from an organic insulating film so that reliability of a display device is increased. The display device includes a transistor, an organic insulating film which is provided over the transistor in order to reduce unevenness due to the transistor, and a capacitor over the organic insulating film. An entire surface of the organic insulating film is not covered with components (a transparent conductive layer and an inorganic insulating film) of the capacitor, and a released gas from the organic insulating film can be released to the outside from exposed part of an upper surface of the organic insulating film.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: December 12, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masatoshi Yokoyama, Shigeki Komori, Manabu Sato, Kenichi Okazaki, Shunpei Yamazaki
  • Patent number: 11837607
    Abstract: A display device includes a liquid crystal element, a transistor, a scan line, and a signal line. The liquid crystal element includes a pixel electrode, a liquid crystal layer, and a common electrode. The scan line and the signal line are each electrically connected to the transistor. The scan line and the signal line each include a metal layer. The transistor is electrically connected to the pixel electrode. A semiconductor layer of the transistor includes a stack of a first metal oxide layer and a second metal oxide layer. The first metal oxide layer includes a region with lower crystallinity than the second metal oxide layer. The transistor includes a first region connected to the pixel electrode. The pixel electrode, the common electrode, and the first region are each configured to transmit visible light. Visible light passes through the first region and the liquid crystal element and exits from the display device.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: December 5, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kenichi Okazaki, Daisuke Kurosaki, Yasutaka Nakazawa, Kazunori Watanabe, Koji Kusunoki
  • Publication number: 20230387217
    Abstract: A novel material is provided. A composite oxide semiconductor includes a first region and a second region. The first region contains indium. The second region contains an element M (the element M is one or more of Ga, Al, Hf, Y, and Sn). The first region and the second region are arranged in a mosaic pattern. The composite oxide semiconductor further includes a third region. The element M is gallium. The first region contains indium oxide or indium zinc oxide. The second region contains gallium oxide or gallium zinc oxide. The third region contains zinc oxide.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 30, 2023
    Inventors: Shunpei YAMAZAKI, Yasuharu HOSAKA, Yukinori SHIMA, Junichi KOEZUKA, Kenichi OKAZAKI
  • Publication number: 20230378371
    Abstract: To improve field-effect mobility and reliability in a transistor including an oxide semiconductor film. A semiconductor device includes a transistor including an oxide semiconductor film. The transistor includes a region where the maximum value of field-effect mobility of the transistor at a gate voltage of higher than 0 V and lower than or equal to 10 V is larger than or equal to 40 and smaller than 150; a region where the threshold voltage is higher than or equal to minus 1 V and lower than or equal to 1 V; and a region where the S value is smaller than 0.3 V/decade.
    Type: Application
    Filed: August 3, 2023
    Publication date: November 23, 2023
    Inventors: Shunpei YAMAZAKI, Junichi KOEZUKA, Kenichi OKAZAKI, Yukinori SHIMA, Shinpei MATSUDA, Haruyuki BABA, Ryunosuke HONDA
  • Patent number: 11817508
    Abstract: A semiconductor device with favorable electrical characteristics is to be provided. A highly reliable semiconductor device is to be provided. A semiconductor device with lower power consumption is to be provided. The semiconductor device includes a gate electrode, a first insulating layer over the gate electrode, a metal oxide layer over the first insulating layer, a pair of electrodes over the metal oxide layer, and a second insulating layer over the pair of electrodes. The first insulating layer includes a first region and a second region. The first region has a region being in contact with the metal oxide layer and containing more oxygen than the second region. The second region has a region containing more nitrogen than the first region. The metal oxide layer has at least a concentration gradient of oxygen in a thickness direction, and the concentration gradient becomes high on a first region side and on a second region side.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: November 14, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Kenichi Okazaki, Yukinori Shima, Yasutaka Nakazawa, Yasuharu Hosaka, Shunpei Yamazaki
  • Publication number: 20230343875
    Abstract: To provide a semiconductor device including a planar transistor having an oxide semiconductor and a capacitor. In a semiconductor device, a transistor includes an oxide semiconductor film, a gate insulating film over the oxide semiconductor film, a gate electrode over the gate insulating film, a second insulating film over the gate electrode, a third insulating film over the second insulating film, and a source and a drain electrodes over the third insulating film; the source and the drain electrodes are electrically connected to the oxide semiconductor film; a capacitor includes a first and a second conductive films and the second insulating film; the first conductive film and the gate electrode are provided over the same surface; the second conductive film and the source and the drain electrodes are provided over the same surface; and the second insulating film is provided between the first and the second conductive films.
    Type: Application
    Filed: June 9, 2023
    Publication date: October 26, 2023
    Inventors: Shunpei YAMAZAKI, Kenichi OKAZAKI, Masahiro KATAYAMA, Masataka NAKADA
  • Publication number: 20230341736
    Abstract: A liquid crystal display device with a high aperture ratio is provided. A liquid crystal display device with low power consumption is provided. The display device includes a display portion and a driver circuit portion. The display portion includes a liquid crystal element, a first transistor, a scan line, and a signal line. The driver circuit portion includes a second transistor. The liquid crystal element includes a pixel electrode, a liquid crystal layer, and a common electrode. Each of the scan line and the signal line is electrically connected to the first transistor. The scan line and the signal line each include a metal layer. The structure of the first transistor is different from that of the second transistor. The first transistor is electrically connected to the pixel electrode. The first transistor includes a first region connected to the pixel electrode. The pixel electrode, the common electrode, and the first region have a function of transmitting visible light.
    Type: Application
    Filed: June 30, 2023
    Publication date: October 26, 2023
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Yukinori SHIMA, Kenichi OKAZAKI, Natsuko TAKASE
  • Patent number: 11799032
    Abstract: A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, and a first conductive layer. The first insulating layer is provided over the semiconductor layer. The first conductive layer is provided over the first insulating layer. The semiconductor layer includes a first region that overlaps with the first conductive layer and the first insulating layer, a second region that does not overlap with the first conductive layer and overlaps with the first insulating layer, and a third region that overlaps with neither the first conductive layer nor the first insulating layer. The semiconductor layer contains a metal oxide. The second region and the third region contain a first element. The first element is one or more elements selected from boron, phosphorus, aluminum, and magnesium.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: October 24, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kenichi Okazaki, Masami Jintyou, Kensuke Yoshizumi