Patents by Inventor Kenichi Yoshida

Kenichi Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200035410
    Abstract: Disclosed herein is an LC filter that includes a conductive substrate, a first capacitive insulating film having one surface covered with the conductive substrate and other surface covered with a first capacitive electrode, a first inductor pattern having one end connected to the first capacitive electrode, a first terminal electrode connected to other end of the first inductor pattern, and a common terminal electrode connected to the conductive substrate.
    Type: Application
    Filed: July 24, 2019
    Publication date: January 30, 2020
    Inventors: Eiko WAKATA, Kenichi YOSHIDA
  • Publication number: 20200013554
    Abstract: In a thin-film capacitor, an electrode terminal layer and an electrode layer of a capacitor portion are connected to electrode terminals by via conductors that is formed to penetrate an insulating layer in a thickness direction thereof, and a short circuit wiring in the thickness direction is realized by the via conductors. In the thin-film capacitor, an increase in the number of terminals in the plurality of electrode terminals is achieved, a decrease in length of a circuit wiring is achieved, and thus a thin-film capacitor with low-ESL has been achieved.
    Type: Application
    Filed: February 13, 2018
    Publication date: January 9, 2020
    Applicant: TDK Corporation
    Inventors: Koichi TSUNODA, Mitsuhiro TOMIKAWA, Kazuhiro YOSHIKAWA, Kenichi YOSHIDA
  • Patent number: 10529495
    Abstract: A thin-film capacitor includes a capacitor section in which electrode layers and dielectric layers are alternately stacked and which includes a hole portion that extends to the electrode layer. In a cross-section which is perpendicular to a stacking surface of the capacitor section and which passes through the hole portion, a side surface of the hole portion extends along a reference line extending in a direction intersecting the stacking surface, the dielectric layer extends up to the reference line toward the hole portion, and a gap is formed between the side surface of the pair electrode layer and the reference line.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: January 7, 2020
    Assignee: TDK CORPORATION
    Inventors: Hiroshi Takasaki, Masahiro Hiraoka, Hitoshi Saita, Kenichi Yoshida
  • Patent number: 10530354
    Abstract: An insulating gate semiconductor device includes an insulating gate semiconductor element, an insulating circuit board, and a main-current path member. A main-current of the insulating gate semiconductor element flows toward a first external terminal in the main-current path member; and a gate-current path member, being patterned so as to have a linearly extending portion arranged in parallel to a linearly extending portion of the main-current path member in a planar pattern on the insulating circuit board, being provided to connect between a second external terminal and a gate electrode of the insulating gate semiconductor element. A current which is induced in the gate-current path member by mutual induction caused by a change in magnetic field implemented by the main-current is used for increasing the gate-current in a turn-on period of the insulating gate semiconductor element.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: January 7, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shinichi Masuda, Shinichi Yoshiwatari, Kenichi Yoshida, Hiroshi Ishida
  • Publication number: 20190378791
    Abstract: An electronic component mounting package includes a semiconductor element which is disposed such that an active surface faces a main surface of a wiring portion, and which is electrically connected to the wiring portion via a first terminal; and a thin film passive element which is disposed between the active surface of the semiconductor element and the main surface of the wiring portion when seen in a lamination direction, and which is electrically connected to the semiconductor element. A part of the first terminal is disposed on an outer side with respect to the thin film passive element in a plan view. A length of the first terminal in the lamination direction disposed on the outer side with respect to the thin film passive element is larger than a thickness of the thin film passive element in the lamination direction.
    Type: Application
    Filed: January 10, 2018
    Publication date: December 12, 2019
    Applicant: TDK Corporation
    Inventors: Kazuhiro YOSHIKAWA, Mitsuhiro TOMIKAWA, Kenichi YOSHIDA
  • Patent number: 10483345
    Abstract: An electronic component embedded substrate includes: a substrate that includes an insulating layer and has a first principal surface and a second principal surface on the opposite side of the first principal surface; and an electronic component that is embedded in the substrate and has a plurality of first terminals provided close to the first principal surface, a plurality of second terminals provided close to the second principal surface, and a capacity part provided between the plurality of first terminals and the plurality of second terminals. The electronic component is configured such that at least a part of the second terminals is embedded in the insulating layer. An insulating member is provided between the neighboring second terminals to be in contact with both of the neighboring second terminals. The insulating member and the insulating layer are formed of materials whose thermal expansion coefficients are different from each other.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: November 19, 2019
    Assignee: TDK CORPORATION
    Inventors: Mitsuhiro Tomikawa, Koichi Tsunoda, Kazuhiro Yoshikawa, Kenichi Yoshida
  • Publication number: 20190304701
    Abstract: A thin-film capacitor satisfies a relationship of CTE1>CTE2>CTE3 regarding a linear expansion coefficient CTE1 of a base, a linear expansion coefficient CTE2 of a capacitance unit, and a linear expansion coefficient CTE3 of a barrier layer. The inventors have newly found that in a case in which such a relationship is satisfied, when a temperature falls from a deposition temperature, cracking occurring in the capacitance unit of the thin-film capacitor is prevented, and cracking occurring in the barrier layer is also prevented.
    Type: Application
    Filed: March 21, 2019
    Publication date: October 3, 2019
    Applicant: TDK CORPORATION
    Inventors: Daiki ISHII, Kazuhiro YOSHIKAWA, Koichi TSUNODA, Mitsuhiro TOMIKAWA, Junki NAKAMOTO, Kenichi YOSHIDA
  • Patent number: 10429269
    Abstract: A building safety verification system and a building safety verification method for estimating a degree of damage of a building after an earthquake occurs are provided. The building safety verification system includes: an inter-story displacement measurement unit which obtains, from measurement data of acceleration sensors which measure accelerations of a plurality of stories in a building, an inter-story displacement of each of the stories; a natural period measurement unit which obtains a natural period of microtremor of the building from measurement data of a micro vibration sensor which measures micro vibration of a highest story of the building or a story near the highest story; and a building safety evaluation unit which evaluates soundness of the building from the inter-story displacement obtained by the inter-story displacement measurement unit and the natural period obtained by the natural period measurement unit.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: October 1, 2019
    Assignee: NTT FACILITIES, INC.
    Inventors: Kenichi Yoshida, Shigeto Nagashima, Toshiya Motohi, Kouzou Toyota, Yoshifumi Sugimura, Wataru Gotou, Maki Mochiduki, Hiroyasu Nishii
  • Publication number: 20190287726
    Abstract: A thin film capacitor includes a capacitance portion in which a plurality of electrode layers and dielectric layers are alternately laminated, a cover layer, an insulating layer, a via hole in which one electrode layer different from an uppermost electrode layer among the plurality of electrode layers is exposed at a bottom surface thereof, and an opening which is provided inside the via hole and in which the one electrode layer is exposed at a bottom surface thereof, and in which the cover layer and the insulating layer are exposed at a side surface. The opening includes a first opening portion which passes through the insulating layer and a second opening portion which is provided below the first opening portion and passes through the cover layer, and when an inner diameter of the first opening portion is D1 and an inner diameter of the second opening portion is D2, D1>D2.
    Type: Application
    Filed: March 15, 2019
    Publication date: September 19, 2019
    Applicant: TDK Corporation
    Inventors: Kazuhiro YOSHIKAWA, Daiki ISHII, Kenichi YOSHIDA
  • Publication number: 20190279823
    Abstract: Provided is a manufacturing method of a thin film capacitor comprising a capacitance portion in which at least one dielectric layer is sandwiched between a pair of electrode layers included in a plurality of electrode layers, the manufacturing method including a lamination process of alternately laminating the plurality of electrode layers and a dielectric film and forming a laminated body which will be the capacitance portion, a first etching process of forming an opening extending in a laminating direction with respect to the laminated body and exposing the dielectric film laminated directly on one of the plurality of electrode layers on a bottom surface of the opening, and a second etching process of exposing the one electrode layer at the bottom surface of the opening. In the second etching process, an etching rate of the one electrode layer is lower than an etching rate of the dielectric film.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 12, 2019
    Applicant: TDK Corporation
    Inventors: Michihiro KUMAGAE, Kazuhiro YOSHIKAWA, Kenichi YOSHIDA, Junki NAKAMOTO, Norihiko MATSUZAKA
  • Patent number: 10392704
    Abstract: A method of providing a coating on a conductor. The coating has a first layer containing palladium and a second layer containing gold from the conductor side. The first layer has an inner layer on the conductor side and an outer layer arranged nearer to the second layer than the inner layer, and the outer layer has a higher phosphorus concentration than the inner layer.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: August 27, 2019
    Assignee: TDK CORPORATION
    Inventors: Kenichi Yoshida, Yuhei Horikawa, Atsushi Sato, Hisayuki Abe
  • Patent number: 10340088
    Abstract: In a thin-film capacitor, an electrode terminal layer is divided into a plurality of parts by a penetration portion, and includes a frame portion as one divided part. The frame portion is disposed along an outer edge of the electrode terminal layer when viewed from the bottom surface side of the electrode terminal layer, and the frame portion can hinder deformation of the electrode terminal layer stretching or warping in a thickness direction or an in-plane direction, whereby such deformation can be prevented. Accordingly, in the thin-film capacitor, the electrode terminal layer is not likely to be deformed and an improvement in strength thereof is achieved.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: July 2, 2019
    Assignee: TDK CORPORATION
    Inventors: Koichi Tsunoda, Mitsuhiro Tomikawa, Kazuhiro Yoshikawa, Kenichi Yoshida
  • Patent number: 10319524
    Abstract: A thin-film capacitor includes electrode layers stacked in a stacking direction; dielectric layers stacked between the electrode layers; an opening portion that includes a side surface penetrating at least a part of the electrode layers and at least a part of the dielectric layers in the stacking direction from a top side and a bottom surface exposing one of the electrode layers; and a wiring portion disposed in the opening portion to be separated from the side surface of the opening portion, and electrically connected to the electrode layer exposed from the bottom surface of the opening portion. The dielectric layer that is stacked immediately on the electrode layer exposed from the bottom surface of the opening portion among the dielectric layers includes an extension portion extending in the opening portion from the side surface of the opening portion to the wiring portion side.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: June 11, 2019
    Assignee: TDK CORPORATION
    Inventors: Kenichi Yoshida, Kazuhiro Yoshikawa, Michihiro Kumagae, Norihiko Matsuzaka, Junki Nakamoto
  • Patent number: 10293762
    Abstract: A vehicle interior part includes a structure in which a soft upholstery material covers a front surface of a base material which is located on an interior side of a vehicle. The soft upholstery material is disposed in a stretched state on the front surface of the base material which is located on the interior side of the vehicle.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: May 21, 2019
    Assignees: TOYOTA IRON WORKS CO., LTD., HAYASHI TELEMPU CO., LTD
    Inventors: Kenji Onuma, Osamu Miyashita, Kenichi Yoshida, Masamori Hirose, Kenichi Uemori, Shintaro Suga
  • Patent number: 10278290
    Abstract: An electronic component embedded substrate 1 includes a substrate 10 having a wiring layer 11 and an insulating layer 12; an electronic component 20 built in the substrate 10, and having a pair of electrode layers 21A and 21B, and a dielectric layer 22; and a stress relieving layer 30 provided closer to the wiring layer 11 than the insulating layer 12 is in the lamination direction, wherein at least part of an end portion of the electronic component 20 on the wiring layer 11 side is in contact with the stress relieving layer 30, wherein at least part of an end portion of the electronic component 20 on the insulating layer 12 side is in contact with the insulating layer 12, and wherein the Young's modulus of the stress relieving layer 30 is lower than the Young's modulus of the electrode layer 21B.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: April 30, 2019
    Assignee: TDK CORPORATION
    Inventors: Kenichi Yoshida, Mitsuhiro Tomikawa
  • Patent number: 10211157
    Abstract: An electronic component includes a first electronic component and a second electronic component that is stacked on the first electronic component. A second electrode layer of the first electronic component includes a plurality of divided electrode layers, and a pair of electrodes of the second electronic component are electrically connected to different electrode layers included in the plurality of electrode layers of the second electrode layer, and a first electrode layer of the first electronic component is divided into a plurality of electrode layers to correspond to the electrode layers which are included in the second electrode layer and which are electrically connected to the pair of electrodes of the second electronic component.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: February 19, 2019
    Assignee: TDK CORPORATION
    Inventors: Kenichi Yoshida, Mitsuhiro Tomikawa, Eiko Wakata
  • Patent number: 10207655
    Abstract: A laminated composite part, which includes a first member having a predetermined mating surface, and a second member that is made of an elastically deformable resin material, that has a plate portion substantially parallel to the mating surface and having a multiplicity of protrusions formed integrally therewith so as to protrude toward the mating surface so that space is created between the plate portion and the mating surface, and that is placed on the first member such that the protrusions contact the mating surface, which has cushioning properties as tip ends of the protrusions are pressed against the mating surface and elastically deformed, and in which one of the first and second members which is located on a design surface side has an engaging projection that projects to a larger extent than the protrusions, and the engaging projection is inserted through an insertion hole formed in the other of the first and second members and is retained in the insertion hole, whereby the first and second members are
    Type: Grant
    Filed: October 18, 2014
    Date of Patent: February 19, 2019
    Assignee: Toyoda Iron Works Co., Ltd.
    Inventors: Kenichi Yoshida, Hideaki Sakai, Osamu Miyashita
  • Patent number: 10205250
    Abstract: A junction structure for electronic device having an excellent bonding strength is provided. A junction structure for electronic device in accordance with one aspect of the present invention includes a first metal layer containing nickel and a second metal layer containing gold, tin, and nickel, while the second metal layer includes an AuSn eutectic phase.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: February 12, 2019
    Assignee: TDK CORPORATION
    Inventors: Kenichi Yoshida, Yuhei Horikawa, Hisayuki Abe
  • Patent number: 10160404
    Abstract: Provided is a multilayer composite interior component in which boundary protrusions (20b) aligned in a row on both sides of a parting line (L) are arranged in a staggered manner so as to bend toward the boundary protrusions (20b) in the row opposite thereto. In this way, even when the boundary protrusions (20b) are separated from the parting line (L) by a predetermined distance (g1, g2) in order to maintain the strength of a divided mold, the boundary protrusions (20b) bend and deform so as to fill in an empty part in the vicinity of the parting line (L) when a surface layer member (16) is pressed by fingers or a hand. As a result, a feeling of unevenness resulting from decreases in reaction force in the vicinity of the parting line (L) is minimized, thus making it possible to obtain a more uniform texture.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: December 25, 2018
    Assignee: Toyoda Iron Works Co., Ltd.
    Inventors: Osamu Miyashita, Kenji Onuma, Kenichi Yoshida
  • Patent number: 10153092
    Abstract: A thin-film capacitor including a stacked body having a lower electrode layer, a plurality of dielectric layers stacked on the lower electrode layer, one or more internal electrode layers interposed between the dielectric layers, and an upper electrode layer that is stacked on the opposite side of the lower electrode layer with the dielectric layers and the internal electrode layers interposed between, and a cover layer that covers the stacked body. The stacked body includes opening portions that have the lower electrode layer, opens upward in a stacking direction, and has a side surface formed to include an inclined surface. The cover layer is stacked on the inclined surface of the stacked body. A curved surface with a predetermined shape is formed on the inclined surface for each pair of layers including the dielectric layer forming the inclined surface and the electrode layer, forming the inclined surface.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: December 11, 2018
    Assignee: TDK CORPORATION
    Inventors: Michihiro Kumagae, Akifumi Kamijima, Norihiko Matsuzaka, Junki Nakamoto, Kazuhiro Yoshikawa, Kenichi Yoshida