Abstract: A direct sensing type semiconductor memory device combines read and write data bus lines in order to conserve real estate. The memory device includes a bit line pair and a sense amplifier connected between the lines of the bit line pair, and a data line pair. A first transistor is connected between a first potential and one of the data lines of the data line pair, and a gate of the first transistor is connected to one of the bit lines of the bit line pair. A second transistor is connected between the first potential and the other one of the data lines, and its gate is connected to the other of the bit lines. A switch circuit is connected between the data line pair and the bit line pair and transfers data from the data line pair to the bit line pair in accordance with a potential difference between the data line pair and the bit line pair.

Abstract: An arrangement to realize the functions of a radio card system in which power is transmitted to perform data communication. According to such arrangement, a delay line and a clock regenerating circuit such as PLL circuit which are previously necessary for demodulation by PSK are not necessary, and thus functions of data communication are realized by minimum hardware construction, size, cost and power consumption. Further, in a data communication system in which electric power transmission using a signal of a frequency fp and digital data communication using a carrier wave of a frequency fs are performed by radio, fs and fp are in the relationship of fs=fp/N (where N is an integer) and a phase shift P when the phase of the carrier wave is modulated by PSK is (M.times.360.degree.)/N (where M, N are integers and P is preferably not equal to 180.degree.).

Abstract: A semiconductor memory device is disclosed, which is supplied with power from a power supply and which includes memory cells and a sense amplifier connected to the cells via bit lines. The memory device further includes a circuit for enabling the sense amplifier in response to a supplied enable signal, and for allowing the sense amplifier to rewrite cell data, read on the bit lines, into the memory cell again in self-refresh mode. The enabling circuit incorporates a noise suppression circuit which suppresses rapid changes in an operation current flowing between the power supply and the sense amplifier in order to minimize power supply related noise.

Abstract: For taking a characteristic impedance matching of signal transmission lines in a package which carries thereon a semiconductor chip with a very high-speed LSI formed thereon, there is provided a semiconductor integrated circuit device wherein one ends of signal transmission lines formed on a main surface of a package substrate are extended up to the position just under pads formed on a main surface of the semiconductor chip and are connected to the pads on the chip electrically through bump electrodes, while opposite ends of the signal transmission lines are extended to the outer peripheral portion of the main surface of the package substrate and outer leads are bonded thereto.

Abstract: A semiconductor memory device is disclosed, which is supplied with power from a power supply and which includes memory cells and a sense amplifier connected to the cells via bit lines. The memory device further includes a circuit for enabling the sense amplifier in response to a supplied enable signal, and for allowing the sense amplifier to rewrite cell data, read on the bit lines, into the memory cell again in self-refresh mode. The enabling circuit incorporates a noise suppression circuit which suppresses rapid changes in an operation current flowing between the power supply and the sense amplifier in order to minimize power supply related noise.

Abstract: A shift register 10 receives serial data and outputs parallel data in synchronism with the timing of the serial data received. A shift register group 20, 21 receives bit outputs of the parallel data from the shift register 10. The number of bits of shift registers 20, 21 in the shift register group is set in a certain condition that corresponds to the bit outputs of the parallel data from the shift register 10. A plurality of coincidence circuits 107, 108 are provided, which detects agreement between a preset data starting pattern and the bit arrangement of the data in the shift register group. A selector 306 selects a set of parallel outputs from the shift register group according to the output signal from the coincidence circuits 107, 108.

Abstract: A flip-flop circuit receives a pair of complementary data signals, then outputs complementary signals corresponding to the pair of complementary data signals. The pair of data signals are also supplied to a driving gate means which outputs a signal corresponding to at least one data signal of the pair of data signals supplied thereto. The driving gate means also comprises at least one try-state gate controlled by a clock signal. An output signal of the driving gate means is held by a memory means, and also outputted as complementary output signals.

Abstract: A low-profile unsaturated polyester resin composition, consisting essentially of (A) an unsaturated polyester, (B) a monomer copolymerizable with the unsaturated polyester, and (C) an A-B type block copolymer comprising an A segment which is a product using vinyl acetate and butyl acrylate as raw materials and a B segment which is a product solely of styrene or a product using styrene and a monomer copolymerizable with styrene as raw materials.

Abstract: An A/D converter apparatus comprises: a sampling signal generating means to generate an oversampling signal and an internal sampling signal; a converter means to convert an input analog signal into a digital signal in synchronism with the oversampling signal; and a decimator means to perform a specified decimation on the digital signal in synchronism with the internal sampling signal; whereby the sampling signal generating means maintains the frequencies of the oversampling signal and the internal sampling signal in a specified relationship.

Abstract: The invention relates to heating containers and, more particularly, to a handy heating container in which food or drink, canned or otherwise, to be heated, such as "sake", coffee, soup, curry, or the like, is set ready for being heated. The heating container has a water discharge device provided on the underside of a solution package containing water or a solution consisting principally of water; and the solution package and a heat generating material are housed in a retainer portion. With this arrangement, exothermic reaction progresses upward from the bottom portion of the heat generating material so that the can is efficiently heated. Furthermore, any water vapor produced is absorbed by the upper portion of the heat generating material so that water vapor jetting through the gap between the can and the container or blowing out of the can is effectively prevented.

Abstract: An amplifier comprising a pair of differential input MISFETs, a current mirror circuit connected between the drains of the differential input MISFETs and a power source terminal, a phase compensation circuit connected to the drain of one of the differential input MISFETs, an output stage amplification circuit amplifying the signal produced at the drain of one of the differential input MISFETs, a phase regulation circuit such as a capacitor connected to the other of the differential input transistors, and a feedback circuit feeding back the output signal produced from the output stage amplification circuit to the other of the differential input MISFETs in order to apply negative feedback to the amplifier. Since the capacitor is provided, the phase of the power source noise can be made substantially equal to the phase of noise occurring at the drain of one of the differential input MISFETs due to the power source noise. Hence, hardly any noise is produced from the output stage amplification circuit.