Abstract: In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.

Abstract: In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.

Abstract: Synchronous memory devices and control methods for performing burst write operations are disclosed. In one embodiment, a synchronous memory device for controlling a burst write operation comprises a first buffer circuit for buffering a first control signal requesting an exit from the burst write operation in synchronization with a clock signal associated with the burst write operation, and a latch circuit for performing a reset in response to the first control signal forwarded by the first buffer circuit, wherein the reset triggers the exit from the burst write operation.

Abstract: The image data with the copy-forgery-inhibited pattern image added and an image area flag signal stored in the hard disk drive are inputted into a thinning filter. A thinning circuit does not perform thinning processing on these pieces of data and outputs the inputted image, as it is. The filter performs processing so that an image of a copy-forgery-inhibited pattern background part may be deleted. A selector selects an image signal not passing through the filter for a latent mark of the copy-forgery-inhibited pattern whose image area flag is set as “Character,” and select an image signal subjected to the processing by the filter for a copy-forgery-inhibited pattern background part whose image area flag is set as “Photograph.” By doing so, it is possible to perform low pass processing on only the copy-forgery-inhibited pattern background part and perform processing of making a latent-mark part emerge.

Abstract: In a storage device having a redundancy remedy function in a block unit having a memory cells array divided in plural blocks, prior to the access operation to individual memory cells in the block, the block address BA for specifying a block is entered, and block redundancy is determined in the entered block address BA, and hence it is not necessary to determine input or redundancy of the block address BA on every occasion of the access operation. As a result, the time to the access operation start to the memory cell can be shortened, and the access speed is enhanced.

Abstract: In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.

Abstract: An oil seal for sealing a hollow rotary shaft in a power transmission apparatus, wherein the rotary shaft is formed with an internal flow passage through which oil flows and constituted such that the oil flies out as the rotary shaft rotates, including: a fixed portion that is fixedly attached to a case of the power transmission apparatus; a seal portion that seals the rotary shaft at a position that is axially offset position from the fixed portion and allows the rotary shaft to rotate; and a radiator portion that is formed from a metallic material between the fixed portion and the seal portion, receives the oil that flies out as the rotary shaft rotates, and dissipates heat generated by the seal portion by exchanging heat with the oil.

Abstract: Synchronous memory devices and control methods for performing burst write operations are disclosed. In one embodiment, a synchronous memory device for controlling a burst write operation comprises a first buffer circuit for buffering a first control signal requesting an exit from the burst write operation in synchronization with a clock signal associated with the burst write operation, and a latch circuit for performing a reset in response to the first control signal forwarded by the first buffer circuit, wherein the reset triggers the exit from the burst write operation.

Abstract: Provided is an interterminal connection structure capable of eliminating the precipitate adhering to the terminal with the installation operation, securing the electrically connected state of the terminal between a pair of members, and easily accommodating to design changes in the spring load. In a cordless handset of a domestic telephone, the conductive state of the terminals employed in the electrical connection between this cordless handset and battery charger is made to contact in a mutually intersecting manner, and, in addition, the terminal on the battery charger side is made to rotate and move pursuant to the installation operation of the cordless handset, and the contact position is gradually moved while maintaining this contact state via such rotating movement. Thus, even if there is a precipitate on the terminals, such precipitate will be chipped off due to the contact movement (sliding), and a loose connection can thereby be prevented.

Abstract: A nonvolatile storage including a plurality of blocks each serving as one unit in erasing operation and performs a plurality of erasing operations successively, the nonvolatile storage comprising: a volatile memory cell array for storing erase setting information on each block, the information indicating whether or not its associated block is a target to be erased; a write amplifier for writing the erase setting information in the volatile memory cell array; a first readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array upon start of the erasing operation; and a second readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array upon start of readout operation.

Abstract: A nonvolatile storage is disclosed which has a plurality of blocks each serving as one unit in erasing operation and performs a plurality of erasing operations successively, the nonvolatile storage comprising: a volatile memory cell array for storing erase setting information on each block, the information indicating whether or not its associated block is a target to be erased; a write amplifier for writing the erase setting information in the volatile memory cell array; a first readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array upon start of the erasing operation; and a second readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array upon start of readout operation.

Abstract: The present invention is a composition that includes granular-grade polytetrafluoroethylene and a plurality of microspheres, where the plurality of microspheres have an average specific gravity less than about 0.9 grams per cubic centimeter.

Abstract: The image data with the copy-forgery-inhibited pattern image added and an image area flag signal stored in the hard disk drive are inputted into a thinning filter. A thinning circuit does not perform thinning processing on these pieces of data and outputs the inputted image, as it is. The filter performs processing so that an image of a copy-forgery-inhibited pattern background part may be deleted. A selector selects an image signal not passing through the filter for a latent mark of the copy-forgery-inhibited pattern whose image area flag is set as “Character,” and select an image signal subjected to the processing by the filter for a copy-forgery-inhibited pattern background part whose image area flag is set as “Photograph.” By doing so, it is possible to perform low pass processing on only the copy-forgery-inhibited pattern background part and perform processing of making a latent-mark part emerge.

Abstract: In a storage device having a redundancy remedy function in a block unit having a memory cells array divided in plural blocks, prior to the access operation to individual memory cells in the block, the block address BA for specifying a block is entered, and block redundancy is determined in the entered block address BA, and hence it is not necessary to determine input or redundancy of the block address BA on every occasion of the access operation. As a result, the time to the access operation start to the memory cell can be shortened, and the access speed is enhanced.

Abstract: The code system is realized by that a plurality of waveforms A and B each having duty ratios of 50% in which only any one of a rising edge and a falling edge is present are combined with each other, and “1” and “0” are allocated to the combined waveform. In accordance with the present invention, both a clock and data can be transmitted at the same time, and can be readily demodulated without using a complex PLL circuit. As a trial manufacture according to the present invention, the demodulator could be realized which could allow variations contained in an input frequency by more than 1 digit under operating voltage of 2 V. The effectiveness of this patent could be confirmed.

Abstract: A semiconductor memory device is arranged so that its circuit area is made smaller and the stored data may be constantly outputted at fast speed. The semiconductor memory device includes a memory cell array and an auxiliary cell array concatenated with word lines on the increasing side of bit-line addresses in the memory cell array. The auxiliary cell array stores data of memory cells in the range from a first bit-line address on a next word-line address to a bit-line address located apart by a predetermined number of bits. A Y-address driver is also included in the semiconductor memory device. The Y-address driver reads data from the auxiliary cell array following the last bit-line address if the read of data pieces at a time ranges from the last bit-line address to the first bit-line address on the next word-line address in the memory cell array.

Abstract: The present invention is a composition that includes granular-grade polytetrafluoroethylene and a plurality of microspheres, where the plurality of microspheres have an average specific gravity less than about 0.9 grams per cubic centimeter.

Abstract: It is an object of the present invention to provide a transformerless charger capable of preventing a human body from receiving an electric shock from a charging terminal, and of making it easy to clean the charging terminal. In order to achieve this object, the transformerless charger of the present invention comprises: a charging terminal for supplying charging voltage to rechargeable electronic equipment; a transformerless power supply circuit for supplying charging voltage to the charging terminal; a flip cover that covers the charging terminal to prevent the charging terminal from being exposed; and a switch that allows or blocks the passage of a current between the charging terminal and the transformerless power supply circuit in synchronization with an opening or closing motion of the flip cover.

Abstract: The present invention is a memory circuit, comprises: a memory cell array including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells disposed in the positions of intersection between the bit lines and the word lines; and a page buffer, which is connected to the bit line and which detects memory cell data by judging with predetermined sense timing the potential of the bit line when a pre-charged bit line potential is discharged in accordance to a cell current of a selected memory cell. Further the sense timing differs in accordance with the position of the selected memory cell in the memory cell array.

Abstract: Provided is an interterminal connection structure capable of eliminating the precipitate adhering to the terminal with the installation operation, securing the electrically connected state of the terminal between a pair of members, and easily accommodating to design changes in the spring load. In a cordless handset of a domestic telephone, the conductive state of the terminals employed in the electrical connection between this cordless handset and battery charger is made to contact in a mutually intersecting manner, and, in addition, the terminal on the battery charger side is made to rotate and move pursuant to the installation operation of the cordless handset, and the contact position is gradually moved while maintaining this contact state via such rotating movement. Thus, even if there is a precipitate on the terminals, such precipitate will be chipped off due to the contact movement (sliding), and a loose connection can thereby be prevented.