Patents by Inventor Kent Kuohua Chang

Kent Kuohua Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140080096
    Abstract: A guided tissue regeneration membrane has a top surface, a bottom surface and the two surfaces are characterized by the plurality of through conical holes. Each of the plurality of through holes has a base opening on the top surface and a tip opening on the bottom surface. The diameter of the base opening is larger than that of the tip opening The guided tissue regeneration membrane is placed between a hard tissue and a soft tissue of gums with the top surface thereof facing the hard tissue so as to hinder the soft tissue from rapidly growing. The tip openings are available for the soft tissue to supply nutrient to the hard tissue therethrough. The hard tissue can grow from the base openings, through the corresponding through holes and to the soft tissue to repair periodontal tissue. In order to achieve a better affinity for cell growth, the guided tissue membrane surface facing the bony surface is coated with a hydrophilic, bioactive and biocompatible nano scaled oxidation layer.
    Type: Application
    Filed: October 16, 2013
    Publication date: March 20, 2014
    Applicant: BioEconeer, Inc.
    Inventor: Kent Kuohua Chang
  • Publication number: 20120065741
    Abstract: A guided tissue regeneration membrane has a top surface, a bottom surface and a plurality of through holes formed through the top and bottom surfaces. Each of the plurality of through holes has a base opening on the top surface and a tip opening on the bottom surface. The diameter of the base opening is larger than that of the tip opening. The guided tissue regeneration membrane is placed between a hard tissue and a soft tissue of gums with the top surface thereof facing the hard tissue so as to hinder the soft tissue from rapidly growing. The tip openings are available for the soft tissue to supply nutrient to the hard tissue therethrough. The hard tissue can grow from the base openings, through the corresponding through holes and to the soft tissue to repair periodontal tissue.
    Type: Application
    Filed: September 13, 2010
    Publication date: March 15, 2012
    Inventors: Chao-Fu Chang, Kent Kuohua Chang
  • Publication number: 20120065604
    Abstract: A degradable hemostatic sponge that can be self-degraded and absorbed by a human body has poly lactic acid as its main material and mixed with a moisture-absorbent material, such as collagen, chitosan, starch and the like, at a specific ratio. Given grinding, mixing and melting steps, the materials using a supercritical fluid as a foaming agent can be used to manufacture the degradable hemostatic sponge having an open-cell microcellular form by a continuous extrusion foaming process. In addition, the present invention also includes a system and a method for manufacturing the degradable hemostatic sponge.
    Type: Application
    Filed: September 13, 2010
    Publication date: March 15, 2012
    Inventors: Chao-Fu Chang, Kent Kuohua Chang
  • Patent number: 7408220
    Abstract: A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. A plurality of first conductive layers are formed between two neighboring first dielectric layers in the same row.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: August 5, 2008
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Jongoh Kim, Yider Wu, Kent-Kuohua Chang
  • Patent number: 7344938
    Abstract: A method of fabricating a memory device is described. During the process of forming the memory cell area and the periphery area of a semiconductor device a photoresist layer is formed on the memory cell area before the spacers are formed on the sidewalls of the gates. Therefore, the memory cell area is prevented from being damaged to mitigate the leakage current problem during the process of forming spacers in the periphery circuit area.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: March 18, 2008
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Kent Kuohua Chang, Jongoh Kim, Yider Wu
  • Publication number: 20070259493
    Abstract: A method of fabricating a memory device is described. During the process of forming the memory cell area and the periphery area of a semiconductor device a photoresist layer is formed on the memory cell area before the spacers are formed on the sidewalls of the gates. Therefore, the memory cell area is prevented from being damaged to mitigate the leakage current problem during the process of forming spacers in the periphery circuit area.
    Type: Application
    Filed: May 7, 2007
    Publication date: November 8, 2007
    Inventors: KENT KUOHUA CHANG, Jongoh Kim, Yider Wu
  • Patent number: 7229876
    Abstract: A method of fabricating a memory device is described. During the process of forming the memory cell area and the periphery area of a semiconductor device a photoresist layer is formed on the memory cell area before the spacers are formed on the sidewalls of the gates. Therefore, the memory cell area is prevented from being damaged to mitigate the leakage current problem during the process of forming spacers in the periphery circuit area.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: June 12, 2007
    Assignee: Macronix International Co., Ltd.
    Inventors: Kent Kuohua Chang, Jongoh Kim, Yider Wu
  • Publication number: 20070026609
    Abstract: A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. A plurality of first conductive layers are formed between two neighboring first dielectric layers in the same row.
    Type: Application
    Filed: August 8, 2006
    Publication date: February 1, 2007
    Inventors: Jongoh Kim, Yider Wu, Kent-Kuohua Chang
  • Publication number: 20070010055
    Abstract: A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. A plurality of first conductive: layers are formed between two neighboring first dielectric layers in the same row.
    Type: Application
    Filed: July 11, 2005
    Publication date: January 11, 2007
    Inventors: Jongoh Kim, Yider Wu, Kent-Kuohua Chang
  • Patent number: 7157333
    Abstract: A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. A plurality of first conductive layers are formed between two neighboring first dielectric layers in the same row.
    Type: Grant
    Filed: July 11, 2005
    Date of Patent: January 2, 2007
    Assignee: Macronix International Co., Ltd.
    Inventors: Jongoh Kim, Yider Wu, Kent-Kuohua Chang
  • Patent number: 7098096
    Abstract: A method of fabricating a multi-bit flash memory, having a control gate, a floating gate, a source region, a drain region and a channel region. An isolation region is formed in the floating gate to partition the floating gate into a plurality of conductive blocks. The conductive blocks are arranged in an array with rows extending from the source region to the drain region. Each row of the array has two conductive blocks. Before any data is written to the flash memory, the channel regions under the conductive blocks of the same row have the same threshold voltage, while the channel regions under the conductive blocks of different rows have different threshold voltage.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: August 29, 2006
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Kent Kuohua Chang
  • Publication number: 20060157774
    Abstract: A memory cell is provided as including a substrate, a tunneling dielectric layer, a charge trapping layer, an inter-gate dielectric layer, a metal gate layer, and a source/drain region. The source/drain region is formed in the substrate besides the gate structure that includes the tunneling dielectric layer, charge trapping layer, inter-gate dielectric layer, and metal gate layer. The tunneling dielectric layer is formed on the substrate, the charge trapping layer is formed on the tunneling dielectric layer, the inter-gate dielectric layer is formed on the charge trapping layer, and the metal gate layer is formed on the inter-gate dielectric layer.
    Type: Application
    Filed: May 10, 2005
    Publication date: July 20, 2006
    Inventor: Kent Kuohua Chang
  • Patent number: 7009245
    Abstract: A fabrication method for a read only memory device with a high dielectric constant tunneling dielectric layer, wherein this method provides forming a tunneling dielectric layer on a substrate, wherein the tunneling dielectric layer is formed with HfSiON or HfOxNy. An electron trapping layer and a top oxide layer are sequentially formed over the tunneling dielectric layer. Thereafter, the oxide layer, the electron trapping layer and the tunneling dielectric layer are patterned to form a plurality of stacked structures, followed by forming doped regions in the substrate between the stacked structures. Buried drain oxide layers are further formed over the surface of the doped regions, followed by forming a patterned conductive layer as the word line for the read only memory device.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: March 7, 2006
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Kent Kuohua Chang
  • Patent number: 6884473
    Abstract: A method for fabricating a metal silicide layer includes forming a dielectric layer on a substrate, followed by forming a polysilicon material conductive layer on the dielectric layer. An adhesion layer is then formed on the conductive layer, wherein the adhesion layer is a nitrogen rich layer or a nitrogen ion implanted layer. A metal silicide layer is then formed on the adhesion layer. The adhesion between the metal silicide layer and the conductive layer is more desirable due the adhesion layer.
    Type: Grant
    Filed: December 24, 2002
    Date of Patent: April 26, 2005
    Assignee: Macronix International Co., Ltd.
    Inventor: Kent Kuohua Chang
  • Patent number: 6867463
    Abstract: A silicon nitride read-only-memory structure is provided. The silicon nitride read-only-memory includes a control gate over a substrate, a source region and a drain region in the substrate on each side of the control gate, a charge-trapping layer between the control gate and the substrate and a channel layer in the substrate underneath the charge-trapping layer and between the source region and the drain region. The charge-trapping layer further includes an isolation region. The isolation region partitions the charge-trapping layer into a source side charge-trapping block and a drain side charge-trapping block so that a two-bit structure is formed.
    Type: Grant
    Filed: December 24, 2002
    Date of Patent: March 15, 2005
    Assignee: Macronix International Co., Ltd.
    Inventor: Kent Kuohua Chang
  • Patent number: 6858506
    Abstract: A manufacturing method for a semiconductor device is provided, wherein a silicon germanium (Si1-xGex; SiGe) layer and a strained silicon layer are sequentially formed on a semiconductor substrate. A gate oxide layer and a gate structure are further formed on the strained silicon layer. The gate structure and the strained silicon layer are heavily doped with n-type dopants to form a compressed gate and source/drain regions, respectively. A cap layer is further formed over the semiconductor substrate, followed by conducting an annealing process. The cap layer is subsequently removed.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: February 22, 2005
    Assignee: Macronix International Co., Ltd.
    Inventor: Kent Kuohua Chang
  • Patent number: 6838345
    Abstract: A fabrication method for a silicon nitride read only memory includes sequentially forming a tunneling oxide layer and a charge capture layer on a substrate. An isolation region is formed in the charge capture layer to partition the charge capture layer into a plurality of charge capture blocks. A stacked dielectric layer is then formed on the charge capture layer and the isolation region. Thereafter, the stacked dielectric layer and the charge capture layer are patterned to expose regions of the substrate for forming bit lines, followed by forming a field oxide layer and a control gate.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: January 4, 2005
    Assignee: Macronix International Co., Ltd.
    Inventor: Kent Kuohua Chang
  • Publication number: 20040262672
    Abstract: A fabrication method for a read only memory device with a high dielectric constant tunneling dielectric layer, wherein this method provides forming a tunneling dielectric layer on a substrate, wherein the tunneling dielectric layer is formed with HfSiON or HfOxNy. An electron trapping layer and a top oxide layer are sequentially formed over the tunneling dielectric layer. Thereafter, the oxide layer, the electron trapping layer and the tunneling dielectric layer are patterned to form a plurality of stacked structures, followed by forming doped regions in the substrate between the stacked structures. Buried drain oxide layers are further formed over the surface of the doped regions, followed by forming a patterned conductive layer as the word line for the read only memory device.
    Type: Application
    Filed: August 17, 2004
    Publication date: December 30, 2004
    Inventor: Kent Kuohua Chang
  • Patent number: 6831851
    Abstract: The mask ROM of the present is comprises by a plurality of word lines arranged in a grid, a plurality of memory units arranged between the word lines, each memory unit having a drain corresponding, a plurality of first bit lines arranged in parallel and extending in a direction diagonal to the word lines and above the drains, a plurality of second bit lines arranged in parallel and extending in a direction diagonal to the word lines and above the drains, a plurality of first nodes alternately arranged on the first bit lines, a plurality of second nodes alternately arranged on the second bit lines and the second nodes and the first nodes are arranged alternately; a plurality of third bit lines joined to the first bit lines, and a plurality of fourth bit lines joined to the second bit lines.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: December 14, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Fuh-Cheng Jong, Kent Kuohua Chang
  • Patent number: 6812521
    Abstract: Dopant of an n-type is deposited in the channel area of a p-type well of isolated gate floating gate NMOS transistors forming the memory cells of a memory device array connected in a NAND gate architecture. The dopant is provided by a tilt angle around the existing floating gate/control gate structure at the stage of the fabrication process where the floating gate/control structure is in existence, the field oxidation step may also have occurred, and implantation of the source and drain dopants may also have occurred. This forms a retrograde n-type distribution away from the direction of the surface of the substrate in the channel, which is also concentrated laterally toward the centerline axis of the gate structure and decreases towards the opposing source and drain regions. This deposition promotes buried-channel-like performance of the NMOS transistors connected in series in the NAND gate memory architecture.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: November 2, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yuesong He, Kent Kuohua Chang, R. Lee Tan