Patents by Inventor Kent Kuohua Chang

Kent Kuohua Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030155605
    Abstract: An EEPROM memory cell with high radiation resistance is provided. The present EEPROM memory cell comprises a semiconductor substrate of a first conductivity, a source having a region of the semiconductor substrate doped to have a second conductivity opposite to the first conductivity, a drain spaced from the source and having a region of the semiconductor substrate doped to have the second conductivity, a channel formed in the space between the source and the drain within the semiconductor substrate, a first oxide layer with a first thickness overlying and covering the channel of the semiconductor substrate, a conducting charge trapping layer formed on the first oxide layer, a second oxide layer with a second thickness more than the first thickness of the first oxide layer, overlying and covering the conducting charge trapping layer and a conducting gate layer formed on the second oxide layer.
    Type: Application
    Filed: February 15, 2002
    Publication date: August 21, 2003
    Applicant: Macronix International Co., Ltd.
    Inventors: Fuh-Cheng Jong, Kent Kuohua Chang
  • Publication number: 20030148564
    Abstract: A method to suppress the short channel effect of a semiconductor device is described. The method provides a substrate having a gate structure formed thereon. A source/drain extension region and a source/drain region formed in the substrate beside the gate structure. A pocket ion implantation process is conducted to form a pocket doped region underneath the source/drain extension region. A rapid thermal process is conducted subsequent to the formation of the source/drain extension region, the source/drain region and the pocket doped region.
    Type: Application
    Filed: March 13, 2002
    Publication date: August 7, 2003
    Inventor: Kent Kuohua Chang
  • Patent number: 6602805
    Abstract: In fabricating nitride read only memory, a zirconium oxide layer has high dielectric constant and a zirconium oxide layer is replaced conventional tunnel oxide layer. Zirconium oxide layer can increase coupling ratio of gate dielectric layer and reliability for nitride read only memory type flash memory is improved. This invention, a substrate is provided and a zirconium oxide layer is formed on substrate by reactive magnetron sputtering and a silicon nitride layer is sandwiched between a zirconium oxide layer and a silicon oxide layer. Then, an ONO layer (oxide-nitride-oxide layer) is formed. The method is using zirconium oxide as gate dielectric can reduce leakage current, increase drain current, improve subthreshold characteristics, and electron and hole mobilities.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: August 5, 2003
    Assignee: Macronix International Co., Ltd.
    Inventor: Kent Kuohua Chang
  • Patent number: 6599801
    Abstract: A method of fabricating NROM memory cell, wherein the NROM device comprises a memory array and a peripheral portion. The fabricating method comprising the steps of: providing a substrate which a oxide layer is formed thereon; forming a peripheral polysilicon layer on the oxide layer; defining a patterned peripheral polysilicon; forming an ONO layer over the substrate in the memory array and the peripheral portion; forming an array polysilicon layer on the ONO layer; and defining a patterned array polysilicon. The method of fabricating NROM memory cell according to the invention can solve the problems of top oxide loss, touch between nitride and polysilicon, and BD over-diffusion.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: July 29, 2003
    Assignee: Macronix International Co., Ltd.
    Inventors: Kent Kuohua Chang, Erh-Kun Lai
  • Patent number: 6589835
    Abstract: A process of manufacturing a flash memory device having a tunnel oxide layer with high reliability, low defect and interface trap by using semi-atmospheric pressure chemical vapor deposition (SPACVD) and tetra-ethyl-ortho-silicate (TEOS) reactant. SAPCVD is performed accompanied with a reaction temperature between about 600° C. and about 750° C. and a reaction pressure between about 340 Torr and about 500 Torr to react TEOS and oxygen.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: July 8, 2003
    Assignee: Macronix International Co., Ltd.
    Inventor: Kent Kuohua Chang
  • Publication number: 20030113989
    Abstract: A semiconductor wafer is provided having both a memory array area and a periphery circuit region defined on the surface of the semiconductor wafer. A gate composed of a silicon oxide layer and a silicon germanium layer is formed on the surface of the periphery circuit region, and a spacer, a source and a drain of the MOS transistor are formed around the gate. Finally, a nickel (Ni) layer is formed on the surface of the source and the drain, and a rapid thermal annealing process (RTA process) with a temperature ranging between 400° C. and 500° C. is performed for forming a silicon nickel layer on the surface of the source and the drain. Additionally, a shallow junction for the source and the drain is formed.
    Type: Application
    Filed: December 14, 2001
    Publication date: June 19, 2003
    Inventor: Kent Kuohua Chang
  • Publication number: 20030113960
    Abstract: A semiconductor wafer is provided having both a memory array area and a periphery circuit region defined on the surface of the semiconductor wafer. A gate composed of a silicon oxide layer and a silicon germanium layer is formed on the surface of the periphery circuit region, and a spacer, a source and a drain of the MOS transistor are formed around the gate. Finally, a nickel (Ni) layer is formed on the surface of the source and the drain, and a rapid thermal annealing process (RTA process) with a temperature ranging between 400° C. and 500° C. is performed for forming a silicon nickel layer on the surface of the source and the drain. Additionally, a shallow junction for the source and the drain is formed.
    Type: Application
    Filed: December 19, 2001
    Publication date: June 19, 2003
    Inventor: Kent Kuohua Chang
  • Patent number: 6580639
    Abstract: The present invention makes use of ion bombardment to amorphize the source and drain regions of a short channel FET prior to implanting. The source/drain implants are then localized to a shallow depth by appropriate choice of implanting conditions, typically employing rather low bombardment voltages of approximately 10 KeV. Amorphous source/drain regions substantially hinder the diffusion of source/drain dopants and thereby reduce the possibility of punchthrough and loss of FET function. Such devices are preferably used in NAND type flash memory devices maintaining proper self-boosting voltages and FET functions even when short channel lengths are employed.
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: June 17, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yue-Song He, Kent Kuohua Chang, Allen U. Huang
  • Patent number: 6566203
    Abstract: A method for preventing electron secondary injection in a pocket implantation process performed on a nitride read only memory (NROM). The NROM has an oxide-nitride-oxide (ONO) layer formed on a silicon substrate. A plurality of bit line masks, arranged in a column, is formed on the surface of the ONO layer. A plurality of N type bit lines is formed in a region of the substrate not covered by the bit line masks. The method starts by performing a pocket implantation process of Indium ions with low energy, high dosage and using an angle nearly parallel to the ONO layer, so as to prevent electron secondary injection. Also, a plurality of P-type ultra-shallow junctions is formed in the region of the substrate not covered by the bit line masks.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: May 20, 2003
    Assignee: Macronix International Co. Ltd.
    Inventors: Kent Kuohua Chang, Samuel Cheng-Sheng Pan
  • Publication number: 20030075738
    Abstract: The present invention provides a twin bit cell flash memory device and its fabricating method. The method is to first form a gate oxide layer on the surface of the silicon substrate followed by forming a polysilicon germanium (Si1−xGex, x=0.05˜1.0) layer on the gate oxide layer. Thereafter, an ion implantation process is performed to form at least one insulating region in the polysilicon germanium layer for separating the polysilicon germanium layer into two isolated conductive regions and forming a twin bit cell structure. Then, a dielectric layer is formed on the polysilicon germanium layer and a photo-etching-process (PEP) is performed to etch portions of the dielectric layer and the polysilicon germanium layer for forming a floating gate of the twin bit cell flash memory. Finally, a control gate is formed over the floating gate.
    Type: Application
    Filed: May 21, 2002
    Publication date: April 24, 2003
    Inventor: Kent Kuohua Chang
  • Patent number: 6551879
    Abstract: A method for forming a semiconductor device that includes defining a substrate to include a peripheral section and a core section, masking the peripheral section of the substrate, growing a first dielectric layer over the core section of the substrate, depositing a first polysilicon layer over the first dielectric layer for forming at least one gate structure, growing a first oxide layer over the first polysilicon layer, depositing a nitride layer over the first oxide layer, implanting oxygen ions into the nitride layer, unmasking the peripheral section of the substrate, and growing a second oxide layer over the nitride layer, wherein the growth rate of the second oxide layer is increased due to the implantation of oxygen ions in the nitride layer.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: April 22, 2003
    Assignee: Macronix International Co., Inc.
    Inventor: Kent Kuohua Chang
  • Patent number: 6548425
    Abstract: The present invention fabricates an oxide-nitride-oxide (ONO) layer of an NROM. A first oxide layer is formed on the surface of the substrate of a semiconductor wafer. Then two CVD processes are performed to respectively form a first nitride layer and a second nitride layer on the surface of the first oxide layer, and the boundary between the second nitride layer and the first nitride layer is so forming an interface. Thereafter, a second oxide layer is formed on the surface of the second nitride layer completing the process of manufacturing the ONO layer. The second nitride layer and the first nitride layer are used as a floating gate of the NROM, and the interface is used as a deep charge trapping center to improve the charge trapping efficiency, and furthermore, to improve the endurance and reliability of the NROM.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: April 15, 2003
    Assignee: Macronix International Co. Ltd.
    Inventors: Kent Kuohua Chang, Uway Tseng
  • Patent number: 6541322
    Abstract: The present invention shows a method of fabricating a MOS transistor on the substrate of a semiconductor wafer and of preventing the gate depletion effects occurring in the MOS transistor. The method involves first forming a silicon oxide layer on the substrate. Then an amorphous silicon layer is formed on the silicon oxide layer followed by forming a silicon germanium (Si1-xGex, x=0.05˜1.0) layer on the amorphous silicon layer. Thereafter, an etching process removes portions of the silicon germanium layer and the amorphous silicon layer so as to form gates of the MOS transistor on the substrate. Finally, a spacer is formed around each gate and a source and a drain of each MOS transistor is formed in the substrate.
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: April 1, 2003
    Assignee: Macronix International Co. Ltd.
    Inventor: Kent Kuohua Chang
  • Patent number: 6538292
    Abstract: A semiconductor wafer comprises a semiconductor substrate of a first conductive type, a source and a drain of a second conductive type positioned in predetermined areas of the semiconductor substrate, and a channel positioned on the surface of the semiconductor substrate between the source and the drain. The memory device contains a first dielectric layer covering the surface of the channel. A conductive layer covers the surface of the first dielectric layer, the conductive layer containing an insulating region for separating the conductive layer so as to form two isolated conductive regions. A second dielectric layer covers the surface of the conductive layer. A gate covers the surface of the second dielectric layer. Each conductive region is used as a charge trapping layer so as to receive and store electrons injected into the conductive region, thus forming a twin bit cell flash memory device.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: March 25, 2003
    Assignee: Macronix International Co. Ltd.
    Inventors: Kent Kuohua Chang, Fuh-Cheng Jong
  • Publication number: 20030006451
    Abstract: A structure of a flash memory having a tunnel oxide layer with high reliability, low defect and interface trap, manufactured by using a process of semi-atmospheric pressure chemical vapor deposition (SPACVD) and tetra-ethyl-ortho-silicate (TEOS) reactant, wherein the SAPCVD process is performed accompanied with a reaction temperature between about 600° C. and about 750° C. and a reaction pressure between about 340 Torr and about 500 Torr to react TEOS and oxygen.
    Type: Application
    Filed: April 24, 2002
    Publication date: January 9, 2003
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Kent Kuohua Chang
  • Publication number: 20030003658
    Abstract: A memory device is formed on a silicon substrate. A blocking layer is thereafter formed to cover a stacked gate of the memory device. A gettering layer is formed on the blocking layer followed by planarizing of the gettering layer to a predetermined thickness. A first barrier layer is then formed on the gettering layer. A contact hole is formed to penetrate through the first barrier layer, the gettering layer and the blocking layer down to the surface of the memory device. Following that, a second barrier layer is created to cover the first barrier layer and the contact hole. Finally, portions of the second barrier layer are etched back to make a barrier spacer on the side wall of the contact hole. Therein, the first barrier layer and the barrier spacer prevent mobile atoms from vertically diffusing and laterally diffusing, respectively, into the memory device.
    Type: Application
    Filed: March 28, 2002
    Publication date: January 2, 2003
    Inventors: Uway Tseng, Ching-Yu Chang, Kent Kuohua Chang
  • Patent number: 6500711
    Abstract: A fabrication method for an interpoly dielectric layer, wherein the method provides a substrate having a first polysilicon layer already formed thereon. An interpoly dielectric layer is then formed on the first polysilicon layer, wherein the interpoly dielectric layer is formed using an argon gas/oxygen gas/ammonia gas plasma, a krypton gas/oxygen gas/ammonia gas plasma, an argon gas/oxygen gas plasma or a krypton gas/oxygen gas plasma. After this, a second polysilicon layer is formed on the interpoly dielectric layer.
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: December 31, 2002
    Assignee: Macronix International Co., Ltd.
    Inventor: Kent Kuohua Chang
  • Patent number: 6498104
    Abstract: In one embodiment, the present invention relates to a method of cleaning a low pressure chemical vapor deposition apparatus having TEOS material build-up therein involving contacting the low pressure chemical vapor deposition apparatus with a composition containing at least one lower alcohol. In another embodiment, the present invention relates to a system for cleaning a low pressure chemical vapor deposition apparatus having TEOS material build-up therein, containing a supply of a composition comprising at least one lower alcohol; an injection port for introducing the composition including at least one lower alcohol into the low pressure chemical vapor deposition apparatus; and a pump/vacuum system for removing crystallized TEOS material build-up from the low pressure chemical vapor deposition apparatus.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: December 24, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Fuodoor Gologhlan, David Chi, Kent Kuohua Chang, Hector Serrato
  • Patent number: 6487114
    Abstract: A method of reading two-bit information in Nitride Read only memory (NROM) cell simultaneously. According to outputted voltage in drain or source of the NROM, it can identify a logical two-bit combination massage of the NROM. The method includes: grounding the source of the NROM; inputting a voltage to the drain of the NROM; inputting a voltage to the gate of the NROM; measuring the outputted current of drain or source; and dividing the outputted current into four different zones, and each zone represents a specific logical two-bit information, which is “0 and 0”, “0 and 1”, “1 and 0”, or “1 and 1”.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: November 26, 2002
    Assignee: Macronix International Co., Ltd.
    Inventors: Fuh-Cheng Jong, Kent Kuohua Chang
  • Patent number: 6486028
    Abstract: A method for fabricating a nitride read only device is disclosed. A trench is formed in a semiconductor substrate. An ion implantation is performed to form a first source/drain region and a second source/drain region within the substrate in the upper corners of the trench, and to form a common source/drain region within the substrate at a bottom of the trench. Next, a trapping layer is formed over the substrate and the trench and a gate conducting layer is formed over the substrate and filling the trench.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: November 26, 2002
    Assignee: Macronix International Co., Ltd.
    Inventors: Kent Kuohua Chang, Yao-Wen Chang