Abstract: A radiation resistant hexagonal gate flash memory cell. The flash memory cell includes a substrate, a source region, a drain region and a gate structure. A channel region is also formed in the substrate between the source region and the drain region. The gate structure is located above the substrate between the source region and the drain region. The gate structure further includes an oxide-nitride-oxide composite layer over the substrate. In a direction perpendicular to the channel, width of the gate structure increases gradually from the source region towards a pre-determined location and decreases towards the drain region thereafter. When the flash memory cell is subjected to radiation illumination, electron-hole pairs thus generated will be injected into the substrate without passing into the nitride layer.

Abstract: A memory device and a fabrication method thereof, wherein the memory device includes a gate oxide layer disposed on a surface of the substrate and a gate disposed on a portion of the gate oxide layer. A buried drain line is located in the substrate beside both sides of the gate and a spacer is disposed beside the sidewalls of the gate. A deep doped region is located in the substrate below a portion of the buried drain line, wherein the buried drain line and the deep doped region together serve as a word line for the memory device. An insulation layer is disposed above the bit line and a word line is disposed above the gate and the insulation layer, perpendicular to a direction of the bit line.

Abstract: A method for fabricating a shallow trench isolation structure includes forming a hard mask layer over a substrate. An ion bombardment step is further performed on the surface of the hard mask layer, followed by forming a patterned photoresist layer on the surface of the hard mask layer. Thereafter, the hard mask layer is patterned using the photoresist layer as an etching mask. An etching process is further performed to form a trench in the substrate. The photoresist layer is then removed, followed by filling an insulation layer in the trench. After this, the hard mask is removed to complete the fabrication of a shallow trench isolation region.

Abstract: A method of boosting wafer-cleaning efficiency and increasing process yield. Different types of process particles are deposited on a test wafer. The test wafer is cleaned in a cleaning operation. The test wafer is scanned to determine the types of process particles that are completely removed and the types of process particles that remain over the test wafer. The results of wafer scanning are used to provide an assessment of the efficiency of the cleaning operation. Operation parameters of the cleaning operation are adjusted to maximize the wafer-cleaning efficiency.

Abstract: A method for reducing random bit failures of flash memory fabrication processes with an HTO film. The random bit failures are caused by HF acid penetration. The HTO film, which functions as an interface reinforcement layer, is formed on a sacrificial layer and a PL1 layer. With the aid of the HTO film, the flash memory is free of acid-corroded seams.

Abstract: The present invention provides a twin bit cell flash memory device and its fabricating method. The method is to first form a gate oxide layer on the surface of the silicon substrate followed by forming a polysilicon germanium (Si1−xGex, x=0.05˜1.0) layer on the gate oxide layer. Thereafter, an ion implantation process is performed to form at least one insulating region in the polysilicon germanium layer for separating the polysilicon germanium layer into two isolated conductive regions and forming a twin bit cell structure. Then, a dielectric layer is formed on the polysilicon germanium layer and a photo-etching-process (PEP) is performed to etch portions of the dielectric layer and the polysilicon germanium layer for forming a floating gate of the twin bit cell flash memory. Finally, a control gate is formed over the floating gate.

Abstract: A method for fabricating a raised source/drain of a semiconductor device is described. A gate structure is formed on a substrate, and then a source/drain with a shallow-junction is formed in the substrate beside the gate structure. A spacer is formed on the sidewalls of the gate structure. Thereafter, an elevated layer is formed on the gate structure and the source/drain with a shallow junction, wherein the elevated layer formed on the source/drain serves as an elevated source/drain layer.

Abstract: A discrete NROM cell, at least comprising: a substrate; a first ON stacking gate and a second ON stacking gate over the substrate, wherein the ON stacking gate is a structure having a nitride layer over a bottom oxide layer; an oxide layer formed over the substrate covering the first and second ON stacking gate; a polysilicon layer formed over the oxide layer; and the source/drain implanted in the substrate and next to the ON stacking gates. The structure of discrete NROM cell of the invention can solve the problem of the electrons being trapped in the nitride layer of NROM cell, and also control the source/drain implant and ON structure at precisely symmetrical positions.

Abstract: A discrete NROM cell, at least comprising: a substrate; a first ONO stacking gate and a second ONO stacking gate over the substrate, wherein the ONO stacking gate is a structure having a nitride layer between two oxide layers; an oxide layer formed over the substrate covering the first and second ONO stacking gates; a polysilicon layer formed over the oxide layer; and the source/drain implanted in the substrate and next to the ONO stacking gates. The structure of discrete NROM cell of the invention can solve the problem of the electrons being trapped in the nitride layer of NROM cell, and also control the source/drain implant and ONO structure at precisely symmetrical positions.

Abstract: The mask ROM of the present is comprises by a plurality of word lines arranged in a grid, a plurality of memory units arranged between the word lines, each memory unit having a drain corresponding, a plurality of first bit lines arranged in parallel and extending in a direction diagonal to the word lines and above the drains, a plurality of second bit lines arranged in parallel and extending in a direction diagonal to the word lines and above the drains, a plurality of first nodes alternately arranged on the first bit lines, a plurality of second nodes alternately arranged on the second bit lines and the second nodes and the first nodes are arranged alternately; a plurality of third bit lines joined to the first bit lines, and a plurality of forth bit lines joined to the second bit lines.

Abstract: A method for fabricating a non-volatile memory having a P-type floating gate is described. A tunneling layer is formed on a substrate and then a first patterned polysilicon layer is formed on the tunneling layer. A buried drain is formed in the substrate beside the first polysilicon layer and then an insulating structure is formed on the tunneling layer on the buried drain. Thereafter, a second polysilicon layer is formed on the first polysilicon layer to constitute a floating gate together with the first polysilicon layer. A P-type ion is implanted into the second polysilicon layer and then a dielectric layer and a control gate are sequentially formed on the floating gate. A thermal process is then performed to make the P-type, ion in the second polysilicon layer diffuse into the first polysilicon layer.

Abstract: A nonvolatile memory cell for prevention from second bit effect comprises a pair of source/drain regions arranged with a channel therebetween, a programmable layer above the channel, and a gate conductor above the programmable layer. The memory cell is characterized in that the programmable layer has a maximum width substantially larger than the boundary widths between the programmable layer and the source/drain regions. The programmable layer comprises a trapping dielectric layer inserted between two insulator layers, and the trapping dielectric preferably comprises a nitride or an oxide having buried polysilicon islands.

Abstract: A method for reducing defects and particles during fabrication of a semiconductor device with an ONO film is disclosed. A substrate divided into a first region and a second region is provided. The first region has a plurality of floating gates and the second region has an oxide layer, a first polysilicon layer, and a second polysilicon layer. An oxide-nitride-oxide (ONO) film is formed over the floating gates and the second polysilicon layer. A patterned photoresist layer masking the first region is formed and a dry etch process is performed to remove the ONO layer, the first polysilicon layer, and the second polysilicon layer within the exposed second region. A series of cleaning steps are performed in a cascade manner.

Abstract: A shallow trench isolation (STI) method for use in semiconductor processes, with the method including the following steps. Having a substrate with a top surface, and forming a trench-patterned mask layer on the top surface to expose an unmasked trench region of the substrate, the mask layer including a pad oxide layer and a silicon nitride layer formed on the pad oxide layer. Etching the unmasked region of the substrate to form a trench on the substrate, depositing an HTO (high temperature oxide) film over the substrate to cover the trench and the mask layer, depositing a dielectric layer to fill the trench and to cover the HTO film, planarizing the dielectric layer to expose the silicon nitride layer, and stripping the silicon nitride.

Abstract: A simplified flash memory fabrication process is disclosed. The method includes the following steps: 1) forming a stacked layer on a substrate in the channel region, and the stacked layer is a polysilicon layer and a sacrificial layer formed atop the polysilicon layer; 2) depositing a dielectric layer to cover the channel region and the bit line region; 3) performing an isotropic dry etching process to etch away a predetermined thickness of the dielectric layer to expose a portion of the sacrificial layer, and at the same time, dividing the dielectric layer into a first portion dielectric layer positioned atop the sacrificial layer and a second portion dielectric layer that is not connected with the first portion dielectric layer; and 4) completely removing the sacrificial layer and the first portion dielectric layer.

Abstract: A method for reducing random bit failures of flash memory fabrication processes with an ISSG film is disclosed. The random bit failures are caused by HF acid penetration. The ISSG film, which functions as a interface reinforcement layer, is formed on a sacrificial layer and a PL1 layer. With the aid of the ISSG film, the flash memory is free of acid-corroded seams.

Abstract: An improved STI method having an ISSG film as an interface reinforcement layer is disclosed. The present invention includes the following steps of forming a trench-patterned mask layer on the top surface of a substrate exposing an unmasked trench region of the substrate. The mask layer is a pad oxide layer and a silicon nitride layer formed on the pad oxide layer. The unmasked region of the substrate is etched to form a trench on the substrate and the silicon nitride layer and the substrate of the trench are simultaneously oxidized to form an ISSG in-situ steam growth (ISSG) film. A dielectric layer is deposited that fills the trench and covers the mask layer. The dielectric layer is planarized to expose the silicon nitride layer, then the silicon nitride is stripped.

Abstract: A memory device and a method for fabricating the same are described. The memory device includes a substrate, buried bit lines, word line structures, a dielectric layer, conductive lines in trenches and self-aligned contacts. The buried bit lines are located in the substrate, and the word line structures are disposed on the substrate crossing over the buried bit lines. Each word line structure consists of a word line, a gate oxide layer, a capping layer and a spacer. Each conductive line is disposed in the dielectric layer and over a buried bit line, and crosses over the capping layers. The dielectric layer is disposed between the word line structures and between the conductive lines. Each self-aligned contact is disposed under a conductive line and between two adjacent word lines to electrically connect the conductive line and the corresponding buried bit line.

Abstract: This invention relates to a method for manufacturing a flash memory, more particularly, to the method for manufacturing the contact in a flash memory with buried conductive line. The method uses an ion implantation process to form buried conductive lines under isolation regions such as shallow trench isolations. Then a dielectric layer is formed on the buried conductive line and the contact, whose top is wider than the bottom, is formed in the dielectric layer. At last, a polysilicon layer is formed in the contact to connect with different devices, which are in the different layers. The buried conductive lines connect neighboring active regions and replace conventional contacts and lead lines connecting the active regions. The bottom of the contact and the buried conductive line are connected with each other.

Abstract: A method for reducing random bit failures of flash memory fabrication processes with an HTO film. The random bit failures are caused by HF acid penetration. The HTO film, which functions as an interface reinforcement layer, is formed on a sacrificial layer and a PL1 layer. With the aid of the HTO film, the flash memory is free of acid-corroded seams.