Abstract: There is provided a novel halogenated zinc phthalocyanine pigment for a color filter, which can form a green color filter having excellent contrast and high luminance. A halogenated zinc phthalocyanine pigment for a color filter shows, in a Raman spectrum, a peak intensity of 3.0% or more at 716±2.2 cm?1 when a peak intensity at 650±10 cm?1 is regarded as 100%.

Abstract: An antenna unit to be used by being installed so as to face window glass of a building, the antenna unit including a radiating element, a reflective member configured to reflect electromagnetic waves radiated from the radiating element toward outside of the building, and a support unit configured to removably support the reflective member. An antenna unit attachment method includes installing an antenna unit so as to face window glass for a building, the antenna unit having a radiating element and a support unit, and supporting a reflective member that reflects electromagnetic waves radiated from the radiating element by the support unit on an outdoor side relative to the radiating element.

Abstract: A protocol chip transmits the request from the host apparatus to a first processor through a first address translation unit. A first processor transmits a response to the request from the host apparatus, to the protocol chip through the first address translation unit. When the first processor stops processing, an instruction to transmit the request from the host apparatus to a second processor is transmitted to the protocol chip. When receiving the instruction to transmit the request from the host apparatus to the second processor, the protocol chip transmits the request from the host apparatus to the second processor through a second address translation unit. The second processor transmits the response to the request from the host apparatus to the protocol chip through the second address translation unit.

Abstract: A first laminated body is worked to form a second laminated body, the first laminated body being formed by laminating prepregs including reinforcing fibers and resin, the second laminated body including a flat portion and a wavy portion, the flat portion being located at at least one of side edge portions of the second laminated body, the wavy portion being located at a portion adjacent to the side edge portion and extending along a longitudinal direction. An intermediate product is formed from the second laminated body by a forming die such that the flat portion becomes a bent portion that is an inside portion whose circumferential length is shorter in a curved portion, and the wavy portion becomes a bent portion that is an outside portion whose circumferential length is longer in the curved portion.

Abstract: A storage system having a plurality of control units that perform read control of data stored in a storage and write control of the data, the storage system comprising, each of the plurality of control units has a processor, a first memory connected to the processor and storing software for executing a process of read control and write control, a network interface for connecting to a control unit network that connects each of the plurality of control units, and a second memory connected to the network interface and storing control information of the data subject to read control and write control and cache data of the storage.

Abstract: A storage system includes a storage controller and a plurality of storage drives. The storage controller holds power management information for managing power supplied to the storage system and power consumption of an operating mounted device of the storage system, and definition information for defining a relationship between power states and power consumption of the plurality of storage drives. The storage controller determines a power budget that can be supplied to the plurality of storage drives, based on the power management information according to a change in a configuration of the storage system, and determines a power state of each of the plurality of storage drives based on the power budget and the definition information.

Abstract: A protocol chip writes a request from a host apparatus to a shared memory. One of the plurality of processors reads the request from the host apparatus from the shared memory through an address translation unit and writes a response to the request to the shared memory through the address translation unit. The protocol chip reads the response from the shared memory and sends the response to the host apparatus. In the case where a first processor reboots, the first processor performs a reboot process of a first address translation unit but does not perform the reboot process of the shared memory. A second processor reads a first request addressed to the first processor from the host apparatus through a second address translation unit and writes a first response to the first request to the shared memory through the second address translation unit.

Abstract: A storage system includes an interface and a data compression system configured to compress reception data from the interface before the data is stored in a storage device. The data compression system is configured to compress the reception data using a first compression algorithm to generate first compressed data, use the number of appearances of each of predetermined code categories included in the first compressed data to estimate a decompression time when a second compression algorithm is used, select a second compression method including compression using the second compression algorithm when the decompression time is equal to or less than a threshold value, and select a first compression method that does not include the compression using the second compression algorithm when the decompression time is greater than the threshold value.

Abstract: The present disclosure is to optimize processes in a storage system. A storage system includes: a first controller including a first computing device and a first memory; a second controller including a second computing device and a second memory; and an interface circuit that transfers data between the first controller and the second controller. The interface circuit reads first compressed data from the second memory. The interface circuit decompresses the first compressed data to generate first uncompressed data, and writes the first uncompressed data into the first memory.

Abstract: A bandwidth between a second processor and a second memory is higher than a bandwidth between a first processor and a first memory. The first memory stores a read command from a host computer. The first processor analyzes a content of the read command, and in accordance with a result of the analysis, requests read data from the second processor. In response to the request from the first processor, the second processor reads the read data from one or more storage drives and stores the read data in the second memory. The second processor notifies the first processor that the read data is stored in the second memory. The first processor transfers the read data read from the second memory, to the host computer without storing the read data in the first memory.

Abstract: To speed up decoding of a range code. A decompression circuit calculates a plurality of candidate bit values for each bit of the N-bit string based on a plurality of possible bit histories of a bit before a K-th bit in parallel for a plurality of bits, and repeatedly selects a correct bit value of the K-th bit from the plurality of candidate bit values based on a correct bit history of the bit before the K-th bit to decode the N-bit string.

Abstract: The storage device includes a first memory, a process device that stores data in the first memory and reads the data from the first memory, and an accelerator that includes a second memory different from the first memory. The accelerator stores compressed data stored in one or more storage drives storing data, in the second memory, decompresses the compressed data stored in the second memory to generate plaintext data, extracts data designated in the process device from the plaintext data, and transmits the extracted designated data to the first memory.

Abstract: The present disclosure is to optimize processes in a storage system. A storage system includes: a first controller including a first computing device and a first memory; a second controller including a second computing device and a second memory; and an interface circuit that transfers data between the first controller and the second controller. The interface circuit reads first compressed data from the second memory. The interface circuit decompresses the first compressed data to generate first uncompressed data, and writes the first uncompressed data into the first memory.

Abstract: To speed up decoding of a range code. A decompression circuit calculates a plurality of candidate bit values for each bit of the N-bit string based on a plurality of possible bit histories of a bit before a K-th bit in parallel for a plurality of bits, and repeatedly selects a correct bit value of the K-th bit from the plurality of candidate bit values based on a correct bit history of the bit before the K-th bit to decode the N-bit string.

Abstract: A storage system includes an interface and a data compression system configured to compress reception data from the interface before the data is stored in a storage device. The data compression system is configured to compress the reception data using a first compression algorithm to generate first compressed data, use the number of appearances of each of predetermined code categories included in the first compressed data to estimate a decompression time when a second compression algorithm is used, select a second compression method including compression using the second compression algorithm when the decompression time is equal to or less than a threshold value, and select a first compression method that does not include the compression using the second compression algorithm when the decompression time is greater than the threshold value.

Abstract: The storage device includes a first memory, a process device that stores data in the first memory and reads the data from the first memory, and an accelerator that includes a second memory different from the first memory. The accelerator stores compressed data stored in one or more storage drives storing data, in the second memory, decompresses the compressed data stored in the second memory to generate plaintext data, extracts data designated in the process device from the plaintext data, and transmits the extracted designated data to the first memory.

Abstract: A bandwidth between a second processor and a second memory is higher than a bandwidth between a first processor and a first memory. The first memory stores a read command from a host computer. The first processor analyzes a content of the read command, and in accordance with a result of the analysis, requests read data from the second processor. In response to the request from the first processor, the second processor reads the read data from one or more storage drives and stores the read data in the second memory. The second processor notifies the first processor that the read data is stored in the second memory. The first processor transfers the read data read from the second memory, to the host computer without storing the read data in the first memory.

Abstract: The present disclosure is to optimize processes in a storage system. A storage system includes: a first controller including a first computing device and a first memory; a second controller including a second computing device and a second memory; and an interface circuit that transfers data between the first controller and the second controller. The interface circuit reads first compressed data from the second memory. The interface circuit decompresses the first compressed data to generate first uncompressed data, and writes the first uncompressed data into the first memory.

Abstract: A storage system includes a plurality of storage controllers and a drive box including one or more non-volatile storage devices. The drive box includes a memory on which reading and writing are performed in a unit different from a unit for reading and writing the one or more non-volatile storage devices, and which stores control information to be used by the plurality of storage controllers, and a memory controller that enables each storage controller of the plurality of storage controllers to exclusively read and write the control information of the memory by arbitrating accesses to the memory from the plurality of storage controllers.

Abstract: Provided is a storage system in which a compression rate of randomly written data can be increased and access performance can be improved. A storage controller 22A includes a cache area 203A configured to store data to be read out of or written into a drive 29. The controller 22A groups a plurality of pieces of data stored in the cache area 203A and input into the drive 29 based on a similarity degree among the pieces of data, selects a group, compresses data of the selected group in group units, and stores the compressed data in the drive 29.