Patents by Inventor Kentaro Shimada

Kentaro Shimada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7917668
    Abstract: A disk controller has a channel adapter having a connection interface to a host computer or a disk drive; a memory adapter for temporarily storing data to be transferred between the host computer and disk drive; a processor adapter for controlling operations of the channel adapter and memory adapter; and a switch adapter for configuring an inner network by interconnecting the channel adapter, memory adapter and processor adapter, wherein the channel adapter, memory adapter, processor adapter and switch adapter each include a DMA controller for performing a communication protocol control of the inner network; and packet multiplex communication is performed among the DMA controllers provided in the adapters. The disk controller can realize a high transfer efficiency and a low cost while retaining a high reliability. A storage system includes an interface unit having an interface with a server or hard drives, a memory unit, a processor unit, and an interconnection.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: March 29, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Mutsumi Hosoya, Naoki Watanabe, Shuji Nakamura, Yasuo Inoue, Kazuhisa Fujimoto, Kentaro Shimada
  • Publication number: 20110004785
    Abstract: A fault-tolerant storage system is provided. The storage system is composed of a controller having a plurality of processors and other units. When an error occurs in any one of the components in the controller, the storage system cuts off an I/O path of the controller, specifies the failed component in the cutoff status, and invalidates the failed component. After invalidating the failed component, the storage system determines whether it is operable only with the normal components, cancels (releases) the cutoff of the I/O path when it determines that it is operable, and resumes operation by rebooting.
    Type: Application
    Filed: September 13, 2010
    Publication date: January 6, 2011
    Applicant: Hitachi, Ltd.
    Inventors: Masanori TAKADA, Shuji Nakamura, Kentaro Shimada
  • Patent number: 7840775
    Abstract: The resources in a storage system including host IF units 101, drive IF units 102, disk drives 103, data transfer engines 105, cache memories 107, and control processors 109 are partitioning targets. A processor 301 in each control processor 109 creates plural logical units by logically partitioning the partitioning target resources, and changes, according to the amount of access from the host computer, the proportion allocated to each logical partition.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: November 23, 2010
    Assignee: Hitachi, Ltd.
    Inventor: Kentaro Shimada
  • Patent number: 7840820
    Abstract: A storage system of the present invention saves power consumption of the storage system and enhances responsiveness by predicting a disk drive that is to be accessed next on the basis of an access request from a host system, and promptly feeding power to the predicted disk drive. A prediction unit predicts the disk drive which is to be accessed next by the host system, by comparing a recent access request from the host system against a past access pattern that is registered in an access pattern record table. A power control unit feeds power from a power unit to the disk drive predicted by the prediction unit.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: November 23, 2010
    Assignee: Hitachi, Ltd.
    Inventor: Kentaro Shimada
  • Patent number: 7831764
    Abstract: Provided is a storage system having a storage device including memory drives formed of the non-volatile memory, a group is constituted by the memory drives whose number is larger than the number of memory drives necessary to provide the memory capacity, the divided storage areas are managed in each of segments that includes at least one of the divided storage areas, the data storage area or the temporary storage area is allocated to the divided storage areas, upon receiving a data write request, the data storage area in which the write data is written and the segment are specified, the updated data is written in the temporary storage area included in the specified segment, the temporary storage area in which the data is written is set as a new data storage area, and data stored in the data storage area is erased and set as a new temporary storage area.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: November 9, 2010
    Assignee: Hitachi, Ltd
    Inventors: Akio Nakajima, Kentaro Shimada, Shuji Nakamura, Nagamasa Mizushima
  • Patent number: 7814270
    Abstract: A storage system is arranged to speed up the operation and easily duplicate data without the capacity of the cache memory being so large even if lots of host computers are connected with the storage system. This storage system includes channel adapters, disk drives, disk adapters, and network switches. Further, the front side cache memories connected with the channel adapters and the back side cache memories connected with the disk adapters are provided as two layered cache system. When a request for writing data is given to the storage system by the host computer, the data is written in both the front side cache memory and the back side cache memory. The write data is duplicated by placing the write data in one of the front side cache memories and one of the back side cache memories or two of the back side cache memories.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: October 12, 2010
    Assignee: Hitachi, Ltd.
    Inventor: Kentaro Shimada
  • Patent number: 7809981
    Abstract: Provided is a storage system superior in fault tolerance. This storage system is composed of a controller having a plurality of processors and other units. When an error occurs in any one of the components in the controller, the storage system cuts off an I/O path of the controller, specifies the failed component in the cutoff status, and invalidates such failed component. Further, after invalidating the failed component, the storage system determines whether it is operable only with the normal components, cancels (releases) the cutoff of the I/O path when it determines that it is operable, and resumes operation by rebooting itself.
    Type: Grant
    Filed: January 10, 2008
    Date of Patent: October 5, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Takada, Shuji Nakamura, Kentaro Shimada
  • Publication number: 20100205359
    Abstract: A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.
    Type: Application
    Filed: April 22, 2010
    Publication date: August 12, 2010
    Applicant: Hitachi, Ltd.
    Inventors: Katsuya Tanaka, Kentaro Shimada
  • Patent number: 7773589
    Abstract: There is provided architecture of a storage system, which has high scalability, low performance ununiformity, and strong fault tolerance, and a control method thereof. The storage system is connected to a host computer. The storage system has four or more nodes. Each node has a host interface unit which is connected to the host computer to communicate with the host computer, and a switch which communicates with the host interface unit. The switch is connected to the switches of other four or less nodes to communicate with the switches of other nodes, such that the nodes are connected to one another in a two-dimensional lattice shape.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: August 10, 2010
    Assignee: Hitachi, Ltd.
    Inventor: Kentaro Shimada
  • Patent number: 7743211
    Abstract: A storage system 1 includes: plural protocol transformation units 10 that transform, to a protocol within the system, a read/write protocol of data exchanged with servers 3 or hard disk groups 2; plural cache control units 21 that include cache memory units 111 storing data read/written with the servers 3 or the hard disk groups 2 and which include the function of controlling the cache memory units 111; and an interconnection network 31 that connects the protocol transformation units 10 and the cache control units 21. In this storage system 1, the plural cache control units 21 are divided into plural control clusters 70, control of the cache memory units 111 is independent inside the control clusters, and a system management unit 60 that manages, as a single system, the plural protocol transformation units 10 and the plural control clusters 70 is connected to the interconnection network 30.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: June 22, 2010
    Inventors: Kazuhisa Fujimoto, Mutsumi Hosoya, Kentaro Shimada, Akira Yamamoto, Naoko Iwami, Yasutomo Yamamoto
  • Patent number: 7743209
    Abstract: There is provided a storage system capable of handling a large amount of control data at low cost in high performance. The storage system includes a cache memory for temporarily storing data read/written between a host computer and a disk array, a CPU for making a control related to data transfer, and a local memory for storing control data utilized by the CPU. The disk array has a first user data storing area for storing user data and a control data storing area for storing all control data. A control unit has a virtualization unit for allocating a memory space of the control data storing area to a virtual address accessible from the CPU, reading the control data specified by the virtual address to a physical address of the local memory, and transferring the control data to the CPU.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: June 22, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Takada, Kentaro Shimada, Shuji Nakamura
  • Publication number: 20100153961
    Abstract: A storage system is comprised of an interface unit 10 which has an interface with a server 3 or hard drives 2, a memory unit 21 which has a cache memory module 126 for storing data to be read from/written to the server 3 or the hard drives 2 and a control information memory module 127 for storing control information of the system, a processor unit 81 which has a microprocessor for controlling the read/write of data between the server 3 and the hard drives 2, and an interconnection 31, wherein the interface unit 10, memory unit 21 and processor unit 81 are interconnected with the interconnection 31.
    Type: Application
    Filed: March 1, 2010
    Publication date: June 17, 2010
    Applicant: HITACHI, LTD.
    Inventors: Kazuhisa Fujimoto, Yasuo Inoue, Mutsumi Hosoya, Kentaro Shimada, Naoki Watanabe
  • Patent number: 7734865
    Abstract: A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: June 8, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Katsuya Tanaka, Kentaro Shimada
  • Publication number: 20100131704
    Abstract: In a storage control apparatus provided therein with a battery-backed-up memory device being a combination of a cache memory of a storage device and a system memory on the side of a CPU, an ASIC (Application-Specific Integrated Circuit) having a virtual window function is provided to a system, and I/O from a front end and/or a back end is performed via a virtual window, thereby making an addition of data integrity code, and performing automatic dual write of data. With such a storage control apparatus provided therein with a battery-backed-up memory being a combination of a CS/DS (Code Storage/Data Storage) and a cache, implemented are protection of block data, and dual write into a Cache (user data, control data) so that the reliability can be kept at the time of data input/output control.
    Type: Application
    Filed: February 26, 2009
    Publication date: May 27, 2010
    Inventors: Akihiro Mannen, Kentaro Shimada
  • Publication number: 20100115329
    Abstract: A storage device in which the MR-IOV is applied to an internal network of a storage controller. Data path failover can be executed in the storage device. The internal network of the storage controller is configured to enable the access of a virtual function (VF) “VF 0:0, 1” of each endpoint device (ED0-ED2) from a root port RP0. Likewise, “VF 1:0, 1” of each endpoint device can be accessed from a root port RP1. In a first data path from the RP0 to ED0 in a normal state, “VF 0:0, 1” and “MVF 0, 0” are connected by VF mapping. When a failure occurs on the first data path, the MR-PCIM executes the VF migration, whereby in the second data path from the RP1 to ED0, “VF 1:0, 1” and “MVF 0, 0” are connected by VF mapping. As a result, failover to the second data path is realized.
    Type: Application
    Filed: December 18, 2008
    Publication date: May 6, 2010
    Inventors: Katsuya TANAKA, Kentaro Shimada
  • Patent number: 7694081
    Abstract: The invention aims at improving the scalability of a storage system using a switch with a small number of ports. A storage system includes a plurality of host connection control units 10 connected to host computers; a plurality of drive control units 12 connected to disk drives 13; and a plurality of 4 by 4 switching units 11 located between each of the host connection control units 10 and each of the drive control units 12, and switching a plurality of paths connecting each host connection control unit 10 and each drive control unit 12, wherein the plurality of 4 by 4 switching units 11 is arranged in multiple stages in the direction of information transmission and the 4 by 4 switching units 11 in each stage are connected so that only two paths are defined from a given host connection control unit 10 from among the host connection control units 10, to every drive control unit 12, and the two paths have no parts in common.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: April 6, 2010
    Assignee: Hitachi, Ltd.
    Inventor: Kentaro Shimada
  • Publication number: 20090274027
    Abstract: The time required for starting up drives in a storage device mounted with both hard disk drives and solid state drives is shortened. A storage controller of the storage device identifies the type (HDD/SSD) of the mounted drives before starting up the drives. The storage controller thereafter performs staggered spinup to the HDDs in several batches. After the startup of HDDs is complete, the storage controller collectively starts up the SSDs. The storage controller determines the drive startup processing based on a pre-set drive startup policy such as reduction of the peak current reduction or shortening of the startup time, and the drive type identification result.
    Type: Application
    Filed: July 15, 2008
    Publication date: November 5, 2009
    Inventors: Katsuya Tanaka, Shuji Nakamura, Kentaro Shimada
  • Patent number: 7594074
    Abstract: To provide a storage system with a cost/performance meeting the system scale, from a small-scale to a large-scale configuration. In the storage system, protocol transformation units and data caching control units are connected to each other through an interconnection, the data caching control units are divided into plural control clusters, each of the control clusters including at least two or more data caching control units, control of a cache memory is conducted independently for each of the control clusters, and one of the plural data caching control units manages, as a single system, protocol transformation units and the plural control clusters based on management information stored in a system management information memory unit.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: September 22, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhisa Fujimoto, Mutsumi Hosoya, Naoki Watanabe, Kentaro Shimada
  • Publication number: 20090216945
    Abstract: Provide is a storage system including one or more disk drives, and one or more cache memories for temporarily storing data read from the disk drives or data to be written to the disk drives, in which: the cache memories includes volatile first memories and non-volatile second memories; and the storage system receives a data write request, stores the requested data in the volatile first memories, selects one of memory areas of the volatile first memories if a total capacity of free memory areas contained in the volatile first memories is less than a predetermined threshold, write data stored in the selected memory area in the non-volatile second memories, and changes the selected memory area to a free memory area. Accordingly, there can be realized capacity enlarging of the cache memory using a non-volatile memory device while realizing a high speed similar to that of a volatile memory device.
    Type: Application
    Filed: April 21, 2008
    Publication date: August 27, 2009
    Inventor: Kentaro SHIMADA
  • Patent number: 7571280
    Abstract: A storage system 1 includes: plural protocol transformation units 10 that transform, to a protocol within the system, a read/write protocol of data exchanged with servers 3 or hard disk groups 2; plural cache control units 21 that include cache memory units 111 storing data read/written with the servers 3 or the hard disk groups 2 and which include the function of controlling the cache memory units 111; and an interconnection network 31 that connects the protocol transformation units 10 and the cache control units 21. In this storage system 1, the plural cache control units 21 are divided into plural control clusters 70, control of the cache memory units 111 is independent inside the control clusters, and a system management unit 60 that manages, as a single system, the plural protocol transformation units 10 and the plural control clusters 70 is connected to the interconnection network 30.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: August 4, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhisa Fujimoto, Mutsumi Hosoya, Kentaro Shimada, Akira Yamamoto, Naoko Iwami, Yasutomo Yamamoto