Patents by Inventor Kentaro Shimada

Kentaro Shimada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8321722
    Abstract: A storage device in which the MR-IOV is applied to an internal network of a storage controller. Data path failover can be executed in the storage device. The internal network of the storage controller is configured to enable the access of a virtual function (VF) “VF 0:0, 1” of each endpoint device (ED0-ED2) from a root port RP0. Likewise, “VF 1:0, 1” of each endpoint device can be accessed from a root port RP1. In a first data path from the RP0 to ED0 in a normal state, “VF 0:0, 1” and “MVF 0, 0” are connected by VF mapping. When a failure occurs on the first data path, the MR-PCIM executes the VF migration, whereby in the second data path from the RP1 to ED0, “VF 1:0, 1” and “MVF 0, 0” are connected by VF mapping. As a result, failover to the second data path is realized.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: November 27, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Katsuya Tanaka, Kentaro Shimada
  • Patent number: 8312314
    Abstract: A fault-tolerant storage system is provided. The storage system is composed of a controller having a plurality of processors and other units. When an error occurs in any one of the components in the controller, the storage system cuts off an I/O path of the controller, specifies the failed component in the cutoff status, and invalidates the failed component. After invalidating the failed component, the storage system determines whether it is operable only with the normal components, cancels (releases) the cutoff of the I/O path when it determines that it is operable, and resumes operation by rebooting.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: November 13, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Takada, Shuji Nakamura, Kentaro Shimada
  • Publication number: 20120254523
    Abstract: Provide is a storage system including one or more disk drives, and one or more cache memories for temporarily storing data read from the disk drives or data to be written to the disk drives, in which: the cache memories includes volatile first memories and non-volatile second memories; and the storage system receives a data write request, stores the requested data in the volatile first memories, selects one of memory areas of the volatile first memories if a total capacity of free memory areas contained in the volatile first memories is less than a predetermined threshold, write data stored in the selected memory area in the non-volatile second memories, and changes the selected memory area to a free memory area. Accordingly, there can be realized capacity enlarging of the cache memory using a non-volatile memory device while realizing a high speed similar to that of a volatile memory device.
    Type: Application
    Filed: June 13, 2012
    Publication date: October 4, 2012
    Inventor: Kentaro SHIMADA
  • Publication number: 20120226861
    Abstract: Provided is a storage controller and method of controlling same which, if part of a storage area of a local memory is used as cache memory, enable an access conflict for access to a parallel bus connected to the local memory to be avoided. A storage controller which exercises control of data between a host system and a storage apparatus, comprising a data transfer control unit which exercises control to transfer the data on the basis of a read/write request from the host system; a cache memory which is connected to the data transfer control unit via a parallel bus; a control unit which is connected to the data transfer control unit via a serial bus; and a local memory which is connected to the control unit via a parallel bus, wherein the control unit decides to assign, from a cache segment of either the cache memory or the local memory, a storage area which stores the data on the basis of a CPU operating rate and a path utilization of the parallel bus connected to the cache memory.
    Type: Application
    Filed: March 3, 2011
    Publication date: September 6, 2012
    Inventors: Yoshihiro Yoshii, Mitsuru Inoue, Kentaro Shimada, Sadahiro Sugimoto
  • Patent number: 8225044
    Abstract: Provide is a storage system including one or more disk drives, and one or more cache memories for temporarily storing data read from the disk drives or data to be written to the disk drives, in which: the cache memories includes volatile first memories and non-volatile second memories; and the storage system receives a data write request, stores the requested data in the volatile first memories, selects one of memory areas of the volatile first memories if a total capacity of free memory areas contained in the volatile first memories is less than a predetermined threshold, write data stored in the selected memory area in the non-volatile second memories, and changes the selected memory area to a free memory area. Accordingly, there can be realized capacity enlarging of the cache memory using a non-volatile memory device while realizing a high speed similar to that of a volatile memory device.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: July 17, 2012
    Assignee: Hitachi, Ltd.
    Inventor: Kentaro Shimada
  • Patent number: 8214595
    Abstract: Provide is a storage system including one or more disk drives, and one or more cache memories for temporarily storing data read from the disk drives or data to be written to the disk drives, in which: the cache memories includes volatile first memories and non-volatile second memories; and the storage system receives a data write request, stores the requested data in the volatile first memories, selects one of memory areas of the volatile first memories if a total capacity of free memory areas contained in the volatile first memories is less than a predetermined threshold, write data stored in the selected memory area in the non-volatile second memories, and changes the selected memory area to a free memory area. Accordingly, there can be realized capacity enlarging of the cache memory using a non-volatile memory device while realizing a high speed similar to that of a volatile memory device.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: July 3, 2012
    Assignee: Hitachi, Ltd.
    Inventor: Kentaro Shimada
  • Patent number: 8209595
    Abstract: The present invention provides means for effectively reducing the amount of data by means of de-duplication in a disk array apparatus having a data guarantee code. A control means for the disk array apparatus that adds a data guarantee code to each logical data block and checks the data guarantee code when reading data has a de-duplication performing function and control means for: generating LA substitution information for a function checking the data guarantee code or read data location address substitution information when performing the de-duplication and storing data; performing the de-duplication using the above-mentioned information when reading data; and thereby avoiding false diagnosis of the data guarantee code check.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: June 26, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Arai, Kentaro Shimada, Shuji Nakamura
  • Publication number: 20120089864
    Abstract: A storage device in which the MR-IOV is applied to an internal network of a storage controller. Data path failover can be executed in the storage device. The internal network of the storage controller is configured to enable the access of a virtual function (VF) “VF 0:0, 1” of each endpoint device (ED0-ED2) from a root port RP0. Likewise, “VF 1:0, 1” of each endpoint device can be accessed from a root port RP1. In a first data path from the RP0 to ED0 in a normal state, “VF 0:0, 1” and “MVF 0, 0” are connected by VF mapping. When a failure occurs on the first data path, the MR-PCIM executes the VF migration, whereby in the second data path from the RP1 to ED0, “VF 1:0, 1” and “MVF 0, 0” are connected by VF mapping. As a result, failover to the second data path is realized.
    Type: Application
    Filed: December 20, 2011
    Publication date: April 12, 2012
    Inventors: Katsuya TANAKA, Kentaro SHIMADA
  • Patent number: 8140749
    Abstract: In a storage control apparatus provided therein with a battery-backed-up memory device being a combination of a cache memory of a storage device and a system memory on the side of a CPU, an ASIC (Application-Specific Integrated Circuit) having a virtual window function is provided to a system. I/O from a front end and/or a back end is performed via a virtual window, thereby making an addition of data integrity code, and performing automatic dual write of data. With such a storage control apparatus provided therein with a battery-backed-up memory being a combination of a CS/DS (Code Storage/Data Storage) and a cache, protection of block data, and dual write into a Cache (user data, control data) are implemented so that the reliability can be kept at the time of data input/output control.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: March 20, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Akihiro Mannen, Kentaro Shimada
  • Publication number: 20120017054
    Abstract: The present invention provides means for effectively reducing the amount of data by means of de-duplication in a disk array apparatus having a data guarantee code. A control means for the disk array apparatus that adds a data guarantee code to each logical data block and checks the data guarantee code when reading data has a de-duplication performing function and control means for: generating LA substitution information for a function checking the data guarantee code or read data location address substitution information when performing the de-duplication and storing data; performing the de-duplication using the above-mentioned information when reading data; and thereby avoiding false diagnosis of the data guarantee code check.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 19, 2012
    Applicant: Hitachi, Ltd.
    Inventors: Masahiro Arai, Kentaro Shimada, Shuji Nakamura
  • Patent number: 8082466
    Abstract: A storage device in which the MR-IOV is applied to an internal network of a storage controller. Data path failover can be executed in the storage device. The internal network of the storage controller is configured to enable the access of a virtual function (VF) “VF 0:0, 1” of each endpoint device (ED0-ED2) from a root port RP0. Likewise, “VF 1:0, 1” of each endpoint device can be accessed from a root port RP1. In a first data path from the RP0 to ED0 in a normal state, “VF 0:0, 1” and “MVF 0, 0” are connected by VF mapping. When a failure occurs on the first data path, the MR-PCIM executes the VF migration, whereby in the second data path from the RP1 to ED0, “VF 1:0, 1” and “MVF 0, 0” are connected by VF mapping. As a result, failover to the second data path is realized.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: December 20, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Katsuya Tanaka, Kentaro Shimada
  • Publication number: 20110296091
    Abstract: Provide is a storage system including one or more disk drives, and one or more cache memories for temporarily storing data read from the disk drives or data to be written to the disk drives, in which: the cache memories includes volatile first memories and non-volatile second memories; and the storage system receives a data write request, stores the requested data in the volatile first memories, selects one of memory areas of the volatile first memories if a total capacity of free memory areas contained in the volatile first memories is less than a predetermined threshold, write data stored in the selected memory area in the non-volatile second memories, and changes the selected memory area to a free memory area. Accordingly, there can be realized capacity enlarging of the cache memory using a non-volatile memory device while realizing a high speed similar to that of a volatile memory device.
    Type: Application
    Filed: August 10, 2011
    Publication date: December 1, 2011
    Inventor: Kentaro SHIMADA
  • Publication number: 20110289277
    Abstract: The present invention obtains with high precision, in a storage system, the effect of additional installation or removal of cache memory, that is, the change of the cache hit rate and the performance of the storage system at that time. For achieving this, when executing normal cache control in the operational environment of the storage system, the cache hit rate when the cache memory capacity has changed is also obtained. Furthermore, with reference to the obtained cache hit rate, the peak performance of the storage system is obtained. Furthermore, with reference to the target performance, the cache memory and the number of disks and other resources that are additionally required are obtained.
    Type: Application
    Filed: March 30, 2009
    Publication date: November 24, 2011
    Inventors: Masanori Takada, Shuji Nakamura, Kentaro Shimada
  • Publication number: 20110271061
    Abstract: Some functions of multiple structural elements are integrated into a specific structural element and the specific structural element controls transmission/reception of signals to/from the respective structural elements. [A storage controller] includes a Frontend I/F Chip, a Backend I/F Chip, a CPU, a memory, and a universal LSI connected to the respective units and transmitting/receiving signals to/from the respective units, wherein the universal LSI is configured by integrating functions of connecting and controlling the respective units and, when connecting to the respective units, the function blocks corresponding to the respective units are validated and become a Frontend control block, a Backend control block, a switch block, a CPU I/F block and a memory control block while the control functions which are not connected are invalidated, and, for the valid functions, signal transmission is performed with the outside of the LSI and, for invalid functions, signal transmission is blocked.
    Type: Application
    Filed: March 25, 2010
    Publication date: November 3, 2011
    Applicant: HITACHI, LTD.
    Inventor: Kentaro Shimada
  • Patent number: 8051367
    Abstract: The present invention provides means for effectively reducing the amount of data by means of de-duplication in a disk array apparatus having a data guarantee code. A control means for the disk array apparatus that adds a data guarantee code to each logical data block and checks the data guarantee code when reading data has a de-duplication performing function and control means for: generating LA substitution information for a function checking the data guarantee code or read data location address substitution information when performing the de-duplication and storing data; performing the de-duplication using the above-mentioned information when reading data; and thereby avoiding false diagnosis of the data guarantee code check.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: November 1, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Arai, Kentaro Shimada, Shuji Nakamura
  • Publication number: 20110246818
    Abstract: A fault-tolerant storage system is provided. The storage system is composed of a controller having a plurality of processors and other units. When an error occurs in any one of the components in the controller, the storage system cuts off an I/O path of the controller, specifies the failed component in the cutoff status, and invalidates the failed component. After invalidating the failed component, the storage system determines whether it is operable only with the normal components, cancels (releases) the cutoff of the I/O path when it determines that it is operable, and resumes operation by rebooting.
    Type: Application
    Filed: May 13, 2011
    Publication date: October 6, 2011
    Applicant: Hitachi, Ltd.
    Inventors: Masanori Takada, Shuji Nakamura, Kentaro Shimada
  • Publication number: 20110231600
    Abstract: A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.
    Type: Application
    Filed: June 1, 2011
    Publication date: September 22, 2011
    Applicant: HITACHI, LTD.
    Inventors: Katsuya Tanaka, Kentaro Shimada
  • Patent number: 7990823
    Abstract: The time required for starting up drives in a storage device mounted with both hard disk drives and solid state drives is shortened. A storage controller of the storage device identifies the type (HDD/SSD) of the mounted drives before starting up the drives. The storage controller thereafter performs staggered spinup to the HDDs in several batches. After the startup of HDDs is complete, the storage controller collectively starts up the SSDs. The storage controller determines the drive startup processing based on a pre-set drive startup policy such as reduction of the peak current reduction or shortening of the startup time, and the drive type identification result.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: August 2, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Katsuya Tanaka, Shuji Nakamura, Kentaro Shimada
  • Patent number: 7970986
    Abstract: A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: June 28, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Katsuya Tanaka, Kentaro Shimada
  • Patent number: 7958391
    Abstract: A fault-tolerant storage system is provided. The storage system is composed of a controller having a plurality of processors and other units. When an error occurs in any one of the components in the controller, the storage system cuts off an I/O path of the controller, specifies the failed component in the cutoff status, and invalidates the failed component. After invalidating the failed component, the storage system determines whether it is operable only with the normal components, cancels (releases) the cutoff of the I/O path when it determines that it is operable, and resumes operation by rebooting.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: June 7, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Takada, Shuji Nakamura, Kentaro Shimada