Patents by Inventor Kentaro Shimada

Kentaro Shimada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220291842
    Abstract: The storage device includes a first memory, a process device that stores data in the first memory and reads the data from the first memory, and an accelerator that includes a second memory different from the first memory. The accelerator stores compressed data stored in one or more storage drives storing data, in the second memory, decompresses the compressed data stored in the second memory to generate plaintext data, extracts data designated in the process device from the plaintext data, and transmits the extracted designated data to the first memory.
    Type: Application
    Filed: May 25, 2022
    Publication date: September 15, 2022
    Inventors: Masahiro TSURUYA, Nagamasa MIZUSHIMA, Tomohiro YOSHIHARA, Kentaro SHIMADA
  • Patent number: 11372552
    Abstract: To provide stable processing performance and perform an appropriate failure processing in a storage device. A storage device includes a plurality of controllers; a plurality of storage drives; and a switch device including a plurality of controller-side ports respectively connected to the plurality of controllers and a plurality of drive-side ports respectively connected to the plurality of storage drives. The switch device performs address translations between the plurality of controller-side ports and the plurality of drive-side ports.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: June 28, 2022
    Assignee: Hitachi, Ltd.
    Inventors: Makio Mizuno, Kentaro Shimada, Ryosuke Matsubara, Midori Kurokawa
  • Publication number: 20220188030
    Abstract: To speed up decoding of a range code. A decompression circuit calculates a plurality of candidate bit values for each bit of the N-bit string based on a plurality of possible bit histories of a bit before a K-th bit in parallel for a plurality of bits, and repeatedly selects a correct bit value of the K-th bit from the plurality of candidate bit values based on a correct bit history of the bit before the K-th bit to decode the N-bit string.
    Type: Application
    Filed: August 31, 2021
    Publication date: June 16, 2022
    Inventors: Nagamasa MIZUSHIMA, Kentaro SHIMADA
  • Patent number: 11360669
    Abstract: The storage device includes a first memory, a process device that stores data in the first memory and reads the data from the first memory, and an accelerator that includes a second memory different from the first memory. The accelerator stores compressed data stored in one or more storage drives storing data, in the second memory, decompresses the compressed data stored in the second memory to generate plaintext data, extracts data designated in the process device from the plaintext data, and transmits the extracted designated data to the first memory.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: June 14, 2022
    Assignee: HITACHI, LTD.
    Inventors: Masahiro Tsuruya, Nagamasa Mizushima, Tomohiro Yoshihara, Kentaro Shimada
  • Publication number: 20220164146
    Abstract: A storage system includes: a controller which includes a processor and a memory; and one or more storage devices. The controller sets a plurality of logical volumes, stores data related to a write request in the memory when the write request is received in the logical volume, and collectively compresses a plurality of pieces of data related to the write request in the memory and writes the compressed data to the storage device. When a plurality of pieces of data related to a plurality of the logical volumes that need to be written to the storage device exist in the memory, the controller selects the plurality of pieces of data in an identical logical volume, and collectively compresses the plurality of pieces of selected data and writes the compressed data in the storage device.
    Type: Application
    Filed: September 13, 2021
    Publication date: May 26, 2022
    Inventors: Masahiro TSURUYA, Norio SHIMOZONO, Akira YAMAMOTO, Kentaro SHIMADA, Takashi NAGAO
  • Patent number: 11274354
    Abstract: The present invention provides a steel material which is excellent in both of the strength (particularly, fatigue strength) and the manufacturability (particularly, bending straightening properties), and thus can be used as an automobile component such as a crankshaft by being formed into a product shape, being subjected to a high strength treatment such as a nitrocarburizing treatment, and then being subjected to the bending straightening.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: March 15, 2022
    Assignees: DAIDO STEEL CO., LTD., HONDA MOTOR CO., LTD.
    Inventors: Ryosuke Ohashi, Ayumi Yamazaki, Yushi Fujinaga, Kentaro Shimada, Ryuta Motani
  • Patent number: 11275505
    Abstract: A data compression system in a storage system compresses data with a first compression method to generate compressed data, determines whether a compression rate of the compressed data is better than a predetermined reference, outputs data obtained by compressing the data by the compression method having a better compression rate than that of the other compression method of the first compression method and a second compression method when it is determined that the compression rate is better than the reference, and outputs data obtained by compressing the data by the compression method having a worse compression rate than that of the other compression method of the first compression method and the second compression method when it is determined that the compression rate is equal to or worse than the reference.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: March 15, 2022
    Assignee: HITACHI, LTD.
    Inventors: Kentaro Shimada, Nagamasa Mizushima
  • Patent number: 11269703
    Abstract: It is detected whether write data has been correctly transmitted to a storage device under a protocol for directly connecting the storage device to a processor. An information processing system including: a processor; a memory; and a storage device, the processor first transmitting to the storage device, a command to invalidate data in a data area and which is designated by a write command, the storage device invalidating the data, the processor second transmitting to the storage device, the write command to write the data into the data area, and the storage device writing the data into the data area in accordance with the write command, validating the data in a data area into which the storage device has been successful in writing the data, and maintaining the data invalidated in a data area into which the storage device has failed in writing the data.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: March 8, 2022
    Assignee: HITACHI, LTD.
    Inventors: Kentaro Shimada, Makio Mizuno
  • Patent number: 11256585
    Abstract: A storage system includes a first storage controller including a plurality of main storage media and one or more processor cores, and a second storage controller including a plurality of main storage media and one or more processor cores and performing communication with the first storage controller. Storage areas of the main storage media in the first storage controller are allocated to an address map. In response to the occurrence of failures in one or mode main storage media of the main storage media of the first storage controller, the first storage controller performs restarting to reallocate the storage areas of the main storage media excluding one or more main storage media having caused the failures to an address map reduced than before the occurrence of the failures. The second storage controller continues operating during the restarting of the first storage controller.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: February 22, 2022
    Assignee: HITACHI, LTD.
    Inventors: Yoshiaki Deguchi, Naoya Okada, Ryosuke Tatsumi, Kentaro Shimada, Sadahiro Sugimoto
  • Publication number: 20210342069
    Abstract: A data compression system in a storage system compresses data with a first compression method to generate compressed data, determines whether a compression rate of the compressed data is better than a predetermined reference, outputs data obtained by compressing the data by the compression method having a better compression rate than that of the other compression method of the first compression method and a second compression method when it is determined that the compression rate is better than the reference, and outputs data obtained by compressing the data by the compression method having a worse compression rate than that of the other compression method of the first compression method and the second compression method when it is determined that the compression rate is equal to or worse than the reference.
    Type: Application
    Filed: September 15, 2020
    Publication date: November 4, 2021
    Applicant: HITACHI, LTD.
    Inventors: Kentaro SHIMADA, Nagamasa MIZUSHIMA
  • Publication number: 20210311664
    Abstract: The storage device includes a first memory, a process device that stores data in the first memory and reads the data from the first memory, and an accelerator that includes a second memory different from the first memory. The accelerator stores compressed data stored in one or more storage drives storing data, in the second memory, decompresses the compressed data stored in the second memory to generate plaintext data, extracts data designated in the process device from the plaintext data, and transmits the extracted designated data to the first memory.
    Type: Application
    Filed: February 10, 2021
    Publication date: October 7, 2021
    Inventors: Masahiro TSURUYA, Nagamasa MIZUSHIMA, Tomohiro YOSHIHARA, Kentaro SHIMADA
  • Patent number: 11119702
    Abstract: To speed up decoding of a range code. A decompression circuit calculates a plurality of candidate bit values for each bit of the N-bit string based on a plurality of possible bit histories of a bit before a K-th bit in parallel for a plurality of bits, and repeatedly selects a correct bit value of the K-th bit from the plurality of candidate bit values based on a correct bit history of the bit before the K-th bit to decode the N-bit string.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: September 14, 2021
    Assignee: HITACHI, LTD.
    Inventors: Nagamasa Mizushima, Kentaro Shimada
  • Publication number: 20210191658
    Abstract: Provided is a storage system in which a compression rate of randomly written data can be increased and access performance can be improved. A storage controller 22A includes a cache area 203A configured to store data to be read out of or written into a drive 29. The controller 22A groups a plurality of pieces of data stored in the cache area 203A and input into the drive 29 based on a similarity degree among the pieces of data, selects a group, compresses data of the selected group in group units, and stores the compressed data in the drive 29.
    Type: Application
    Filed: August 14, 2020
    Publication date: June 24, 2021
    Inventors: Nagamasa MIZUSHIMA, Tomohiro YOSHIHARA, Kentaro SHIMADA
  • Publication number: 20210109661
    Abstract: To provide stable processing performance and perform an appropriate failure processing in a storage device. A storage device includes a plurality of controllers; a plurality of storage drives; and a switch device including a plurality of controller-side ports respectively connected to the plurality of controllers and a plurality of drive-side ports respectively connected to the plurality of storage drives. The switch device performs address translations between the plurality of controller-side ports and the plurality of drive-side ports.
    Type: Application
    Filed: December 18, 2020
    Publication date: April 15, 2021
    Inventors: Makio MIZUNO, Kentaro SHIMADA, Ryosuke MATSUBARA, Midori KUROKAWA
  • Patent number: 10970237
    Abstract: A first storage controller includes a first processor, a first memory, and a first switch having a first port. A second storage controller includes a second processor, a second memory, and a second switch having a second port. A storage system connects the first port and the second port by a first link. The first processor and the first switch are connected by a second link configured to transfer user data and a third link configured to transfer control data. The second processor and the second switch are connected by a fourth link configured to transfer user data and a fifth link configured to transfer control data. The first port and the second port transfer the control data in preference to the user data on the first link.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: April 6, 2021
    Assignee: HITACHI, LTD.
    Inventors: Katsuya Tanaka, Kentaro Shimada
  • Publication number: 20210034482
    Abstract: A storage system includes a first storage controller including a plurality of main storage media and one or more processor cores, and a second storage controller including a plurality of main storage media and one or more processor cores and performing communication with the first storage controller. Storage areas of the main storage media in the first storage controller are allocated to an address map. In response to the occurrence of failures in one or mode main storage media of the main storage media of the first storage controller, the first storage controller performs restarting to reallocate the storage areas of the main storage media excluding one or more main storage media having caused the failures to an address map reduced than before the occurrence of the failures. The second storage controller continues operating during the restarting of the first storage controller.
    Type: Application
    Filed: March 17, 2020
    Publication date: February 4, 2021
    Applicant: Hitachi, Ltd.
    Inventors: Yoshiaki DEGUCHI, Naoya OKADA, Ryosuke TATSUMI, Kentaro SHIMADA, Sadahiro SUGIMOTO
  • Publication number: 20210034250
    Abstract: To provide stable processing performance and perform an appropriate failure processing in a storage device. A storage device includes a plurality of controllers; a plurality of storage drives; and a switch device including a plurality of controller-side ports respectively connected to the plurality of controllers and a plurality of drive-side ports respectively connected to the plurality of storage drives. The switch device performs address translations between the plurality of controller-side ports and the plurality of drive-side ports.
    Type: Application
    Filed: March 13, 2020
    Publication date: February 4, 2021
    Inventors: Makio MIZUNO, Kentaro SHIMADA, Ryosuke MATSUBARA, Midori KUROKAWA
  • Patent number: 10901626
    Abstract: To provide stable processing performance and perform an appropriate failure processing in a storage device. A storage device includes a plurality of controllers; a plurality of storage drives; and a switch device including a plurality of controller-side ports respectively connected to the plurality of controllers and a plurality of drive-side ports respectively connected to the plurality of storage drives. The switch device performs address translations between the plurality of controller-side ports and the plurality of drive-side ports.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: January 26, 2021
    Assignee: HITACHI, LTD.
    Inventors: Makio Mizuno, Kentaro Shimada, Ryosuke Matsubara, Midori Kurokawa
  • Publication number: 20200401346
    Abstract: A storage system includes a plurality of storage controllers and a drive box including one or more non-volatile storage devices. The drive box includes a memory on which reading and writing are performed in a unit different from a unit for reading and writing the one or more non-volatile storage devices, and which stores control information to be used by the plurality of storage controllers, and a memory controller that enables each storage controller of the plurality of storage controllers to exclusively read and write the control information of the memory by arbitrating accesses to the memory from the plurality of storage controllers.
    Type: Application
    Filed: February 26, 2020
    Publication date: December 24, 2020
    Inventors: Kentaro SHIMADA, Akira YAMAMOTO, Katsuya TANAKA
  • Patent number: 10795608
    Abstract: A memory stores: a communication driver that is a software program which runs in an operating system and communicates with a host; and a storage service program that is a software program which runs on the operating system and controls retention of data by a storage apparatus as a storage. The processor is capable of configuring a plurality of queue pairs which transmit information in inter-process communication between the communication driver and the storage service program, and the processor further configures command distribution information which associates a queue pair and a logical volume with each other, specifies a queue pair corresponding to a logical volume that is an access destination of a command requested by the host, and enqueues a command request of the command to the specified queue pair.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: October 6, 2020
    Assignee: HITACHI, LTD.
    Inventors: Hirotoshi Akaike, Kentaro Shimada, Kazushi Nakagawa