Abstract: Efficient communication between storage controllers can be performed. A storage system includes one or more backend switches that connect a first processor, a second processor, and one or more storage devices to each other. Each backend switch identifies a destination of a frame by referring to the frame received from the first processor. In a case where the destination of the frame is the second processor, each backend switch translates a first address, included in the frame, for specifying a location on the second memory in an address space of the first processor, into a second address for specifying the location on the second memory in an address space of the second processor, and transfers the frame including the second address to the second storage controller.

Abstract: Provided is a storage system that includes a plurality of storage devices; a controller that controls the storage device including a processor and a memory; and a data transfer path connecting each of the storage devices to the controller. The storage device is divided into a plurality of groups. The controller specifies the storage device belonging to each of the plurality of groups among the plurality of storage devices connected via the plurality of independent data transfer paths, receives an access request to specify the storage device to be accessed, and designates the different data transfer paths for each group of the specified storage devices. The storage device performs data transfer by a connection-less protocol according to the designated data transfer path.

Abstract: A first storage controller includes a first processor, a first memory, and a first switch having a first port. A second storage controller includes a second processor, a second memory, and a second switch having a second port. A storage system connects the first port and the second port by a first link. The first processor and the first switch are connected by a second link configured to transfer user data and a third link configured to transfer control data. The second processor and the second switch are connected by a fourth link configured to transfer user data and a fifth link configured to transfer control data. The first port and the second port transfer the control data in preference to the user data on the first link.

Abstract: It is detected whether write data has been correctly transmitted to a storage device under a protocol for directly connecting the storage device to a processor. An information processing system including: a processor; a memory; and a storage device, the processor first transmitting to the storage device, a command to invalidate data in a data area and which is designated by a write command, the storage device invalidating the data, the processor second transmitting to the storage device, the write command to write the data into the data area, and the storage device writing the data into the data area in accordance with the write command, validating the data in a data area into which the storage device has been successful in writing the data, and maintaining the data invalidated in a data area into which the storage device has failed in writing the data.

Abstract: A storage system includes: a memory for caching of data according to input and output to a storage device; and a CPU connected to the memory. The memory includes: a DRAM high in access performance; and an SCM identical in a unit of access to the DRAM, the SCM being lower in access performance than the DRAM. The CPU determines whether to perform caching to the DRAM or the SCM, based on the data according to input and output to the storage device, and caches the data into the DRAM or the SCM, based on the determination.

Abstract: Efficient communication between storage controllers can be performed. A storage system includes one or more backend switches that connect a first processor, a second processor, and one or more storage devices to each other. Each backend switch identifies a destination of a frame by referring to the frame received from the first processor. In a case where the destination of the frame is the second processor, each backend switch translates a first address, included in the frame, for specifying a location on the second memory in an address space of the first processor, into a second address for specifying the location on the second memory in an address space of the second processor, and transfers the frame including the second address to the second storage controller.

Abstract: Efficient communication between storage controllers can be performed. A storage system includes one or more backend switches that connect a first processor, a second processor, and one or more storage devices to each other. Each backend switch identifies a destination of a frame by referring to the frame received from the first processor. In a case where the destination of the frame is the second processor, each backend switch translates a first address, included in the frame, for specifying a location on the second memory in an address space of the first processor, into a second address for specifying the location on the second memory in an address space of the second processor, and transfers the frame including the second address to the second storage controller.

Abstract: Provided is a storage system that includes a plurality of storage devices; a controller that controls the storage device including a processor and a memory; and a data transfer path connecting each of the storage devices to the controller. The storage device is divided into a plurality of groups. The controller specifies the storage device belonging to each of the plurality of groups among the plurality of storage devices connected via the plurality of independent data transfer paths, receives an access request to specify the storage device to be accessed, and designates the different data transfer paths for each group of the specified storage devices. The storage device performs data transfer by a connection-less protocol according to the designated data transfer path.

Abstract: Efficient communication between storage controllers can be performed. A storage system includes one or more backend switches that connect a first processor, a second processor, and one or more storage devices to each other. Each backend switch identifies a destination of a frame by referring to the frame received from the first processor. In a case where the destination of the frame is the second processor, each backend switch translates a first address, included in the frame, for specifying a location on the second memory in an address space of the first processor, into a second address for specifying the location on the second memory in an address space of the second processor, and transfers the frame including the second address to the second storage controller.

Abstract: A memory stores: a communication driver that is a software program which runs in an operating system and communicates with a host; and a storage service program that is a software program which runs on the operating system and controls retention of data by a storage apparatus as a storage. The processor is capable of configuring a plurality of queue pairs which transmit information in inter-process communication between the communication driver and the storage service program, and the processor further configures command distribution information which associates a queue pair and a logical volume with each other, specifies a queue pair corresponding to a logical volume that is an access destination of a command requested by the host, and enqueues a command request of the command to the specified queue pair.

Abstract: A metal component structure includes a metal ball and a metal component. The metal ball has an outer diameter. The metal component includes a hole into which the metal ball is press-fitted. The hole includes a central axis, an opening edge, a stopper, and a tapered part. The metal ball is inserted into the hole through the opening edge. The stopper is provided between the opening edge and a center of the metal ball in a direction of the central axis and has an inner diameter smaller than the outer diameter of the metal ball. The tapered part is provided from the opening edge toward the stopper and has an inner diameter decreasing from the opening edge toward the stopper.

Abstract: A system including flash memory modules and a system controller. Each flash memory module includes flash memory chips and a memory controller to manage a plurality of blocks in the plurality of flash memory chips. The blocks are units for erasing data stored in the flash memory chips. The system controller performs wear leveling by exchanging data between a first flash memory module and a second flash memory module of the flash memory modules.

Abstract: A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.

Abstract: A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.

Abstract: A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.

Abstract: Some functions of multiple structural elements are integrated into a specific structural element. The specific structural element controls transmission/reception of signals to/from the respective structural elements. A storage controller includes a Frontend I/F (Interface) Chip, Backend I/F Chip, CPU (Central Processing Unit), memory, and universal LSI (Large Scale Integrated Circuit) connected to the respective units, and transmitting/receiving signals to/from the respective units. The universal LSI is configured by integrating functions of connecting and controlling the respective units, and when connecting to the respective units, the function blocks corresponding to the respective units are validated and become a Frontend control block, a Backend control block, a switch block, a CPU I/F block and a memory control block while the control functions which are not connected are invalidated.

Abstract: A storage system uses a plurality of flash memory modules and a storage controller. Each of the plurality of flash memory modules comprises a memory controller and at least one flash memory chip. The memory controller manages a plurality of blocks provided with the at least one flash memory chip and controls a first wear-leveling process for leveling erase counts between the plurality of blocks. The storage controller, coupled to the plurality of flash memory modules, controls data sent from a host computer to be sent to a flash memory module of the plurality of flash memory modules. The storage controller controls a second wear-leveling process exchanging data between at least one block of a first flash memory module of the plurality of flash memory modules and at least one block of a second flash memory module of the plurality of flash memory modules.

Abstract: A storage includes: host interface units; file control processors which receives a file input/output request and translates the file input/output request into a data input/output request; file control memories which store translation control data; groups of disk drives; disk control processors; disk interface units which connect the groups of disk drives and the disk control processors; cache memories; and inter-processor communication units. The storage logically partitions these devices to cause the partitioned devices to operate as two or more virtual NASs.

Abstract: Provided is a storage controller and method of controlling same which, if part of a storage area of a local memory is used as cache memory, enable an access conflict for access to a parallel bus connected to the local memory to be avoided. A storage controller which exercises control of data between a host system and a storage apparatus, comprising a data transfer control unit which exercises control to transfer the data on the basis of a read/write request from the host system; a cache memory which is connected to the data transfer control unit via a parallel bus; a control unit which is connected to the data transfer control unit via a serial bus; and a local memory which is connected to the control unit via a parallel bus, wherein the control unit decides to assign, from a cache segment of either the cache memory or the local memory, a storage area which stores the data on the basis of a CPU operating rate and a path utilization of the parallel bus connected to the cache memory.

Abstract: The present invention obtains with high precision, in a storage system, the effect of additional installation or removal of cache memory, that is, the change of the cache hit rate and the performance of the storage system at that time. For achieving this, when executing normal cache control in the operational environment of the storage system, the cache hit rate when the cache memory capacity has changed is also obtained. Furthermore, with reference to the obtained cache hit rate, the peak performance of the storage system is obtained. Furthermore, with reference to the target performance, the cache memory and the number of disks and other resources that are additionally required are obtained.