Patents by Inventor Kentaro Shimada

Kentaro Shimada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10901626
    Abstract: To provide stable processing performance and perform an appropriate failure processing in a storage device. A storage device includes a plurality of controllers; a plurality of storage drives; and a switch device including a plurality of controller-side ports respectively connected to the plurality of controllers and a plurality of drive-side ports respectively connected to the plurality of storage drives. The switch device performs address translations between the plurality of controller-side ports and the plurality of drive-side ports.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: January 26, 2021
    Assignee: HITACHI, LTD.
    Inventors: Makio Mizuno, Kentaro Shimada, Ryosuke Matsubara, Midori Kurokawa
  • Publication number: 20200401346
    Abstract: A storage system includes a plurality of storage controllers and a drive box including one or more non-volatile storage devices. The drive box includes a memory on which reading and writing are performed in a unit different from a unit for reading and writing the one or more non-volatile storage devices, and which stores control information to be used by the plurality of storage controllers, and a memory controller that enables each storage controller of the plurality of storage controllers to exclusively read and write the control information of the memory by arbitrating accesses to the memory from the plurality of storage controllers.
    Type: Application
    Filed: February 26, 2020
    Publication date: December 24, 2020
    Inventors: Kentaro SHIMADA, Akira YAMAMOTO, Katsuya TANAKA
  • Patent number: 10795608
    Abstract: A memory stores: a communication driver that is a software program which runs in an operating system and communicates with a host; and a storage service program that is a software program which runs on the operating system and controls retention of data by a storage apparatus as a storage. The processor is capable of configuring a plurality of queue pairs which transmit information in inter-process communication between the communication driver and the storage service program, and the processor further configures command distribution information which associates a queue pair and a logical volume with each other, specifies a queue pair corresponding to a logical volume that is an access destination of a command requested by the host, and enqueues a command request of the command to the specified queue pair.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: October 6, 2020
    Assignee: HITACHI, LTD.
    Inventors: Hirotoshi Akaike, Kentaro Shimada, Kazushi Nakagawa
  • Patent number: 10789196
    Abstract: Efficient communication between storage controllers can be performed. A storage system includes one or more backend switches that connect a first processor, a second processor, and one or more storage devices to each other. Each backend switch identifies a destination of a frame by referring to the frame received from the first processor. In a case where the destination of the frame is the second processor, each backend switch translates a first address, included in the frame, for specifying a location on the second memory in an address space of the first processor, into a second address for specifying the location on the second memory in an address space of the second processor, and transfers the frame including the second address to the second storage controller.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: September 29, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Katsuya Tanaka, Kentaro Shimada, Akira Yamamoto, Sadahiro Sugimoto
  • Patent number: 10732872
    Abstract: Provided is a storage system that includes a plurality of storage devices; a controller that controls the storage device including a processor and a memory; and a data transfer path connecting each of the storage devices to the controller. The storage device is divided into a plurality of groups. The controller specifies the storage device belonging to each of the plurality of groups among the plurality of storage devices connected via the plurality of independent data transfer paths, receives an access request to specify the storage device to be accessed, and designates the different data transfer paths for each group of the specified storage devices. The storage device performs data transfer by a connection-less protocol according to the designated data transfer path.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: August 4, 2020
    Assignee: HITACHI, LTD.
    Inventors: Shotaro Shintani, Kentaro Shimada, Makio Mizuno, Sadahiro Sugimoto
  • Publication number: 20200226078
    Abstract: A first storage controller includes a first processor, a first memory, and a first switch having a first port. A second storage controller includes a second processor, a second memory, and a second switch having a second port. A storage system connects the first port and the second port by a first link. The first processor and the first switch are connected by a second link configured to transfer user data and a third link configured to transfer control data. The second processor and the second switch are connected by a fourth link configured to transfer user data and a fifth link configured to transfer control data. The first port and the second port transfer the control data in preference to the user data on the first link.
    Type: Application
    Filed: September 5, 2019
    Publication date: July 16, 2020
    Applicant: Hitachi, Ltd.
    Inventors: Katsuya Tanaka, Kentaro Shimada
  • Publication number: 20200159605
    Abstract: It is detected whether write data has been correctly transmitted to a storage device under a protocol for directly connecting the storage device to a processor. An information processing system including: a processor; a memory; and a storage device, the processor first transmitting to the storage device, a command to invalidate data in a data area and which is designated by a write command, the storage device invalidating the data, the processor second transmitting to the storage device, the write command to write the data into the data area, and the storage device writing the data into the data area in accordance with the write command, validating the data in a data area into which the storage device has been successful in writing the data, and maintaining the data invalidated in a data area into which the storage device has failed in writing the data.
    Type: Application
    Filed: September 4, 2019
    Publication date: May 21, 2020
    Applicant: Hitachi, Ltd.
    Inventors: Kentaro Shimada, Makio Mizuno
  • Publication number: 20200133836
    Abstract: A storage system includes: a memory for caching of data according to input and output to a storage device; and a CPU connected to the memory. The memory includes: a DRAM high in access performance; and an SCM identical in a unit of access to the DRAM, the SCM being lower in access performance than the DRAM. The CPU determines whether to perform caching to the DRAM or the SCM, based on the data according to input and output to the storage device, and caches the data into the DRAM or the SCM, based on the determination.
    Type: Application
    Filed: August 8, 2019
    Publication date: April 30, 2020
    Inventors: Nagamasa MIZUSHIMA, Sadahiro SUGIMOTO, Kentaro SHIMADA
  • Publication number: 20190347236
    Abstract: Efficient communication between storage controllers can be performed. A storage system includes one or more backend switches that connect a first processor, a second processor, and one or more storage devices to each other. Each backend switch identifies a destination of a frame by referring to the frame received from the first processor. In a case where the destination of the frame is the second processor, each backend switch translates a first address, included in the frame, for specifying a location on the second memory in an address space of the first processor, into a second address for specifying the location on the second memory in an address space of the second processor, and transfers the frame including the second address to the second storage controller.
    Type: Application
    Filed: July 29, 2019
    Publication date: November 14, 2019
    Inventors: Katsuya TANAKA, Kentaro SHIMADA, Akira YAMAMOTO, Sadahiro SUGIMOTO
  • Patent number: 10402361
    Abstract: Efficient communication between storage controllers can be performed. A storage system includes one or more backend switches that connect a first processor, a second processor, and one or more storage devices to each other. Each backend switch identifies a destination of a frame by referring to the frame received from the first processor. In a case where the destination of the frame is the second processor, each backend switch translates a first address, included in the frame, for specifying a location on the second memory in an address space of the first processor, into a second address for specifying the location on the second memory in an address space of the second processor, and transfers the frame including the second address to the second storage controller.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: September 3, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Katsuya Tanaka, Kentaro Shimada, Akira Yamamoto, Sadahiro Sugimoto
  • Publication number: 20190258599
    Abstract: Provided is a storage system that includes a plurality of storage devices; a controller that controls the storage device including a processor and a memory; and a data transfer path connecting each of the storage devices to the controller. The storage device is divided into a plurality of groups. The controller specifies the storage device belonging to each of the plurality of groups among the plurality of storage devices connected via the plurality of independent data transfer paths, receives an access request to specify the storage device to be accessed, and designates the different data transfer paths for each group of the specified storage devices. The storage device performs data transfer by a connection-less protocol according to the designated data transfer path.
    Type: Application
    Filed: February 27, 2017
    Publication date: August 22, 2019
    Applicant: HITACHI, LTD.
    Inventors: Shotaro SHINTANI, Kentaro SHIMADA, Makio MIZUNO, Sadahiro SUGIMOTO
  • Publication number: 20180314666
    Abstract: Efficient communication between storage controllers can be performed. A storage system includes one or more backend switches that connect a first processor, a second processor, and one or more storage devices to each other. Each backend switch identifies a destination of a frame by referring to the frame received from the first processor. In a case where the destination of the frame is the second processor, each backend switch translates a first address, included in the frame, for specifying a location on the second memory in an address space of the first processor, into a second address for specifying the location on the second memory in an address space of the second processor, and transfers the frame including the second address to the second storage controller.
    Type: Application
    Filed: April 23, 2018
    Publication date: November 1, 2018
    Inventors: Katsuya TANAKA, Kentaro SHIMADA, Akira YAMAMOTO, Sadahiro SUGIMOTO
  • Publication number: 20180285021
    Abstract: A memory stores: a communication driver that is a software program which runs in an operating system and communicates with a host; and a storage service program that is a software program which runs on the operating system and controls retention of data by a storage apparatus as a storage. The processor is capable of configuring a plurality of queue pairs which transmit information in inter-process communication between the communication driver and the storage service program, and the processor further configures command distribution information which associates a queue pair and a logical volume with each other, specifies a queue pair corresponding to a logical volume that is an access destination of a command requested by the host, and enqueues a command request of the command to the specified queue pair.
    Type: Application
    Filed: February 19, 2016
    Publication date: October 4, 2018
    Inventors: Hirotoshi AKAIKE, Kentaro SHIMADA, Kazushi NAKAGAWA
  • Publication number: 20170173660
    Abstract: A metal component structure includes a metal ball and a metal component. The metal ball has an outer diameter. The metal component includes a hole into which the metal ball is press-fitted. The hole includes a central axis, an opening edge, a stopper, and a tapered part. The metal ball is inserted into the hole through the opening edge. The stopper is provided between the opening edge and a center of the metal ball in a direction of the central axis and has an inner diameter smaller than the outer diameter of the metal ball. The tapered part is provided from the opening edge toward the stopper and has an inner diameter decreasing from the opening edge toward the stopper.
    Type: Application
    Filed: November 11, 2016
    Publication date: June 22, 2017
    Applicant: HONDA MOTOR CO., LTD.
    Inventors: Hirokazu TOCHIKI, Kentaro SHIMADA
  • Patent number: 9286210
    Abstract: A system including flash memory modules and a system controller. Each flash memory module includes flash memory chips and a memory controller to manage a plurality of blocks in the plurality of flash memory chips. The blocks are units for erasing data stored in the flash memory chips. The system controller performs wear leveling by exchanging data between a first flash memory module and a second flash memory module of the flash memory modules.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: March 15, 2016
    Assignee: HITACHI, LTD.
    Inventors: Katsuya Tanaka, Kentaro Shimada
  • Publication number: 20140325127
    Abstract: A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.
    Type: Application
    Filed: July 8, 2014
    Publication date: October 30, 2014
    Inventors: Katsuya Tanaka, Kentaro Shimada
  • Patent number: 8788745
    Abstract: A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: July 22, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Katsuya Tanaka, Kentaro Shimada
  • Publication number: 20130232297
    Abstract: A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.
    Type: Application
    Filed: March 26, 2013
    Publication date: September 5, 2013
    Applicant: Hitachi, Ltd.
    Inventors: Katsuya Tanaka, Kentaro Shimada
  • Patent number: 8489826
    Abstract: Some functions of multiple structural elements are integrated into a specific structural element. The specific structural element controls transmission/reception of signals to/from the respective structural elements. A storage controller includes a Frontend I/F (Interface) Chip, Backend I/F Chip, CPU (Central Processing Unit), memory, and universal LSI (Large Scale Integrated Circuit) connected to the respective units, and transmitting/receiving signals to/from the respective units. The universal LSI is configured by integrating functions of connecting and controlling the respective units, and when connecting to the respective units, the function blocks corresponding to the respective units are validated and become a Frontend control block, a Backend control block, a switch block, a CPU I/F block and a memory control block while the control functions which are not connected are invalidated.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: July 16, 2013
    Assignee: Hitachi, Ltd.
    Inventor: Kentaro Shimada
  • Patent number: 8429340
    Abstract: A storage system uses a plurality of flash memory modules and a storage controller. Each of the plurality of flash memory modules comprises a memory controller and at least one flash memory chip. The memory controller manages a plurality of blocks provided with the at least one flash memory chip and controls a first wear-leveling process for leveling erase counts between the plurality of blocks. The storage controller, coupled to the plurality of flash memory modules, controls data sent from a host computer to be sent to a flash memory module of the plurality of flash memory modules. The storage controller controls a second wear-leveling process exchanging data between at least one block of a first flash memory module of the plurality of flash memory modules and at least one block of a second flash memory module of the plurality of flash memory modules.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: April 23, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Katsuya Tanaka, Kentaro Shimada