Abstract: An antifuse bank (200) for an integrated circuit. The antifuse bank (200) includes a plurality of word lines (246) and digit lines (244) disposed to form an array. The antifuse bank (200) also includes a plurality of antifuse cells (230). Each antifuse cell (230) includes an antifuse (242) that is programmable to one of two fixed states. Each antifuse cell (230) also includes an access device (240) coupled to one of the word lines (246) and one of the digit lines (244) and coupled to the antifuse (242) of the antifuse cell (230). The antifuse bank (200) further includes an addressing circuit (248, 250) coupled to the array that selects an antifuse (242) of the array to be accessed. The antifuse bank (200) also includes a sensing circuit (228) coupled to the array that senses the state of the selected antifuse (242).

Abstract: The provision of an isolation gate connecting unassociated active areas of adjacent transistors formed in a semiconductor substrate provides effective isolation of the adjacent transistors with no additional process steps required. The isolation gate is tied to a reference to ensure that a channel between the unassociated active areas is not formed, and effective isolation is provided. The adjacent transistors are cross coupled to form sense amplifiers for dynamic random access memory devices.

Abstract: A method for forming a semiconductor device comprises the steps of providing a semiconductor die having a plurality of pads thereon with at least one bond wire electrically coupled with one of the pads and providing a holder having a cavity therein. The die is placed in the cavity, then a layer of encapsulation is formed within the cavity to cover the die. Subsequently, the encapsulated die is removed from the cavity.

Abstract: A memory device module in a package having externally accessible contacts includes multiple integrated memory circuits accessible to external circuitry exclusively through the contacts. An accessing circuit for each memory circuit accesses memory cells in the memory circuit for communication with the external circuitry. Each accessing circuit can be enabled to access redundant memory cells instead of inoperative memory cells by an enabling signal. An enabling circuit for each accessing circuit can output the enabling signal in response to receiving a unique set of input signals from external circuitry. Each unique set is selected with fuses in each enabling circuit, and includes row and column address strobe signals and a data signal. Upon receiving its unique set, one of the enabling circuits advantageously enables its associated accessing circuit to access redundant memory cells without the accessing circuits of the other memory circuits also being so enabled.

Abstract: A helper flip-flop device is coupled to a pair of I/O DIGIT lines in a DC bias current sensing based dynamic random access memory (DRAM) device for ensuring that one of the DIGIT lines returns to as low a voltage as possible following a memory access. A sense amplifier is coupled to the I/O lines to amplify the differential voltage appearing on the lines following access of a memory cell. The helper flip-flop, when activated at the same time the DC bias is removed, sinks current from the low line to ground, effectively reducing its voltage to near ground to allow faster release of the row access signal.

Abstract: An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable pads to one of the MCM's reference voltage pins. By applying a supply voltage to the test mode enable pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a reference voltage applied to the test mode enable pads through the reference voltage pins and the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging.

Abstract: An array of memory cells are arranged in rows and columns. The array includes a plurality of cell plates that are each coupled to at least one of the memory cells. A generator produces a bias voltage. A plurality of isolation circuits are each coupled between the generator and one or more of the cell plates. Each isolation circuit provides the bias voltage to the cell plate or plates to which the isolation circuit is coupled. The cell plates may be coupled to memory cells from a plurality of the columns. Additionally, each of the isolation circuits may selectively provide, in response to a control signal, the bias voltage to the cell plate or plates to which the isolation circuit is coupled.

Abstract: A system for validating mapped signal generation permits identifying deficiencies in dynamic random access memory testing. As an example application of mapped signals consider memory testing. Memory tests such as stripe and checkerboard pattern tests frequently involve topological maps in order to permit use of the same memory test system and test program on memory devices and systems having different characteristics. An effective memory test exercises a memory cell by storing data therein which is of opposite physical polarity to data stored in physically adjacent cells. Topological maps account for variation in polarity of stored data depending on the address of a cell and variation due to the physical layout of cells which may not necessarily place consecutively addressed cells in physical proximity. A fixture for dynamic random access memory testing according to the present invention includes a battery, a signal multiplexer, and mode switching circuitry.

Abstract: A multilayer decoupling capacitor structure is disclosed, having a first decoupling capacitor with one electrode formed in a conductively doped silicon substrate and a second electrode made of conductively doped polysilicon. A third bifurcated conductive layer disposed above the second electrode in conjunction with a fourth conductive layer above the third layer form a second and third decoupling capacitor. The first decoupling capacitor serves to decouple circuitry associated with dynamic random access memory cells, while the second and third decoupling capacitors provide decoupling for further circuitry.

Abstract: An antifuse bank (200) for an integrated circuit. The antifuse bank (200) includes a plurality of word lines (246) and digit lines (244) disposed to form an array. The antifuse bank (200) also includes a plurality of antifuse cells (230). Each antifuse cell (230) includes an antifuse (242) that is programmable to one of two fixed states. Each antifuse cell (230) also includes an access device (240) coupled to one of the word lines (246) and one of the digit lines (244) and coupled to the antifuse (242) of the antifuse cell (230). The antifuse bank (200) further includes an addressing circuit (248, 250) coupled to the array thin selects an antifuse (242) of the array to be accessed. The antifuse bank (200) also includes a sensing circuit (228) coupled to the array that senses the state of the selected antifuse (242).

Abstract: A SIMM (single in-line memory module) board is provided with a plurality of integrated semiconductor memory or other integrated semiconductor circuit devices which include, as a part of each integrated circuit device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the device to the board. By connecting the on-chip capacitors of the integrated circuit devices in parallel, sufficient capacitance is provided to stabilize current to all of the integrated circuit devices.

Abstract: A helper flip-flop device is coupled to a pair of I/O DIGIT lines in a DC bias current sensing based dynamic random access memory (DRAM) device for ensuring that one of the DIGIT lines returns to as low a voltage as possible following a memory access. A sense amplifier is coupled to the I/O lines to amplify the differential voltage appearing on the lines following access of a memory cell. The helper flip-flop, when activated at the same time the DC bias is removed, sinks current from the low line to ground, effectively reducing its voltage to near ground to allow faster release of the row access signal.

Abstract: A circuit, responsive to the application of primary power, generates signals to establish the initial state of a logic circuit. Generated signals are interposed on the logic circuit's input signal line until initialization is complete. After initialization, the logic circuit's input signal line is recoupled for normal operation.

Abstract: A system for validating mapped signal generation permits identifying deficiencies in dynamic random access memory testing. As an example application of mapped signals consider memory testing. Memory tests such as stripe and checkerboard pattern tests frequently involve topological maps in order to permit use of the same memory test system and test program on memory devices and systems having different characteristics. An effective memory test exercises a memory cell by storing data therein which is of opposite physical polarity to data stored in physically adjacent cells. Topological maps account for variation in polarity of stored data depending on the address of a cell and variation due to the physical layout of cells which may not necessarily place consecutively addressed cells in physical proximity. A fixture for dynamic random access memory testing according to the present invention includes a battery, a signal multiplexer, and mode switching circuitry.

Abstract: A circuit, responsive to the application of primary power, generates signals to establish the initial state of a logic circuit. Generated signals are interposed on the logic circuit's input signal line until initialization is complete. After initialization, the logic circuit's input signal line is recoupled for normal operation.

Abstract: A new inverting output driver circuit is disclosed that reduces electron injection into the substrate by the drain of the circuit's pull-up field effect transistor. This is accomplished by adding additional circuitry that allows the gate voltage of the pull-up transistor to track the source voltage. The output circuit makes use of an inverter having an output node (hereinafter the intermediate node) coupled to V.sub.CC through a first P-channel FET, and to ground through first and second series coupled N-channel FETs, respectively. The gates of the P-channel FET and the first N-channel FET are coupled to and controlled by an input node. The inverter output node controls the gate of third N-channel FET, through which a final output node is coupled to V.sub.CC. The intermediate node is coupled to the final output node through a fourth N-channel FET, the gate of which is held at ground potential. The gate of the second N-channel FET is coupled to V.sub.

Abstract: The invention is directed to a concept to use a 3-dimensional DRAM capacitor as a one-time non-volatile programming element (programmable antifuse) to make redundancy repair and/or to select other options on a DRAM. The programmable element of the present invention provides some significant advantages, such as a lower programming voltage, which allows use of the DRAM's existing operating supply, and requiring only half of the operating voltage to test the element once programming is accomplished. The lower programming voltage allows for redundancy repair of defective DRAM cells (or selecting other options) to be made after the DRAM die is packaged including after it is installed at a customer's site.

Abstract: A SIMM (single in-line memory module) board is provided with a plurality of semiconductor memory devices which include, as a part of each memory device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the memory device to the board. By connecting the on-chip capacitors of the memory devices in parallel, sufficient capacitance is provided to stabilize current to all of the memory devices.

Abstract: An extensive network of N-channel transistor formed capacitor, with one node tie directly to V.sub.cc power bus and the other node directly V.sub.ss power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 .mu.F.

Abstract: A new inverting output driver circuit is disclosed that reduces electron injection into the substrate by the drain of the circuit's pull-up field effect transistor. This is accomplished by adding additional circuitry that allows the gate voltage of the pull-up transistor to track the source voltage. The output circuit makes use of an inverter having an output node (hereinafter the intermediate node) coupled to V.sub.CC through a first P-channel FET, and to ground through first and second series coupled N-channel FETs, respectively. The gates of the P-channel FET and the first N-channel FET are coupled to and controlled by an input node. The inverter output node controls the gate of third N-channel FET, through which a final output node is coupled to V.sub.CC. The intermediate node is coupled to the final output node through a fourth N-channel FET, the gate of which is held at ground potential. The gate of the second N-channel FET is coupled to V.sub.