Abstract: A method and apparatus for electrolytic plating of selected areas of printed circuit board traces is disclosed. The method is characterized by its elimination of the need for plating bus bars and plating contacts on the printed circuit board to facilitate a spot-plating process. In one embodiment, a printed circuit board substrate is provided which is at least partially conductive, such that a plating voltage may be applied to any one or more points on the substrate during a spot plating operation. In another embodiment, the substrate material is initially partially conductive, but following the spot-plating operation, is subjected to a curing treatment or the like to cause degeneration of the substrate's conductivity. Carbon-impregnated polimid, partially-cured polyimid, FR4 or FR5, with appropriate contaminants introduced therein are contemplated as materials suitable for a printed circuit board substrate in accordance with the invention.

Abstract: The present invention provides a method and apparatus for writing a programmable conductor random access memory (PCRAM) element. After a read operation of the memory element a complement logical state from that read is written back to the memory element. In one embodiment the memory element is then again written back to its original state. In another embodiment logic circuitry keeps track of whether the original logic state or its complement are stored in the memory element so that during the next read the stored logic will be correctly read.

Abstract: A semiconductor device system for coupling with external circuitry. The system includes a control signal on a carrier substrate. A semiconductor device is attached to the carrier substrate with an impedance matching device coupled to the control signal.

Abstract: An integrated circuit is provided with one or more connectors which allow an opto-electric device to be mounted on the integrated circuit directly on top of or underneath of it. Multiple opto-electric device interface regions can be defined on the integrated circuit such that an opto-electric device can be connected in a variety of directions or such that multiple opto-electric devices can be connected. In addition, an opto-electric device interface may be provided that causes the opto-electric device's leads to be directed to the corresponding integrated circuit lead in the shortest possible distance regardless of how the opto-electric device is positioned. Also disclosed is a substrate-mounted optical transmission system that may be used in connection with the opto-electric device.

Abstract: A stereolithographic method and apparatus for forming polymeric structures comprising a plurality of overlying layers, each layer formed by polymerizing a thin layer of liquid photopolymer on a prior layer. Crevices formed at the layer interfaces are filled by a stereolithographic method comprising lifting the multilayered structure from the liquid photopolymer, draining excess liquid therefrom, tilting the structure to provide an acute angle of incidence between an incident radiation beam and a side wall of the object, and applying radiation to the crevice to polymerize at least the surface of a quantity of liquid photopolymer therein. The structure may then be subjected to a separate final full cure to fully harden the structure. An exemplary use is the packaging of electronic components and the like.

Abstract: A heat sink is provided for use with stacks of integrated chips. The heat sink includes a thermally conductive body having a heat absorbing section which is inserted within the chip stack, and heat transfer and dissipating sections which are located outside of the chip stack.

Abstract: A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.

Abstract: A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.

Abstract: The formation of routing traces on an external surface of a semiconductor device, such as a flip-chip, which has a plurality of ball or bump sites patterned in specific locations, wherein the ball or bump sites are in electrical communication with external communication traces which are used to route signals from the flip-chip integrated circuitry. Such external communication traces generally result in unused space on the exterior surface of the flip-chip. This unused space can be utilized for forming routing traces to connect portions of the internal circuitry of the flip-chip rather than forming such routing traces internally, for forming routing traces to connect two or more semiconductor dice, or for forming routing traces for use as repair mechanisms.

Abstract: The formation of routing traces on an external surface of a semiconductor device, such as a flip-chip, which has a plurality of ball or bump sites patterned in specific locations, wherein the ball or bump sites are in electrical communication with external communication traces which are used to route signals from the flip-chip integrated circuitry. Such external communication traces generally result in unused space on the exterior surface of the flip-chip. This unused space can be utilized for forming routing traces to connect portions of the internal circuitry of the flip-chip rather than forming such routing traces internally, for forming routing traces to connect two or more semiconductor dice, or for forming routing traces for use as repair mechanisms.

Abstract: The present invention provides a method and apparatus for writing a programmable conductor random access memory (PCRAM) element. After a read operation of the memory element a complement logical state from that read is written back to the memory element. In one embodiment the memory element is then again written back to its original state. In another embodiment logic circuitry keeps track of whether the original logic state or its complement are stored in the memory element so that during the next read the stored logic will be correctly read.

Abstract: A semiconductor device system for coupling with external circuitry. The system includes a control signal on a carrier substrate. A semiconductor device is attached to the carrier substrate with an impedance matching device coupled to the control signal.

Abstract: A method for producing a monolithic, seamless, polymeric housing structure for a micromachine uses a stereolithographic method to produce the structure layer by layer by exposing sequentially formed films of photopolymer to a beam of electromagnetic radiation scanned over patterns of locations corresponding to at least partially superimposed layers of the housing structure. The housing structure may include openings through which movable elements such as shafts and linkages may extend, and may provide sealed passage for electrical conductors therethrough from the micromachine to the exterior of the housing structure. Complex housing structures including closed or almost closed chambers and interior partition walls as well as interior passages of complex configuration may be formed to accommodate individual components or component assemblies.

Abstract: A method and apparatus for electrolytic plating of selected areas of printed circuit board traces is disclosed. The method is characterized by its elimination of the need for plating bus bars and plating contacts on the printed circuit board to facilitate a spot-plating process. In one embodiment, a printed circuit board substrate is provided which is at least partially conductive, such that a plating voltage may be applied to any one or more points on the substrate during a spot plating operation. In another embodiment, the substrate material is initially partially conductive, but following the spot-plating operation, is subjected to a curing treatment or the like to cause degeneration of the substrate's conductivity. Carbon-impregnated polyimide, partially-cured polyimide, FR4 or FR5, with appropriate contaminants introduced therein are contemplated as materials suitable for a printed circuit board substrate in accordance with the invention.

Abstract: An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable bond pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable bond pads to one of the MCM's ground pins. By applying a supply voltage to the test mode enable bond pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a ground voltage applied to the test mode enable bond pads through the ground pins so the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging.

Abstract: Provided herein are vertical nanotube semiconductor devices and methods for making the same. An embodiment of the semiconductor devices comprises a vertical transistor/capacitor cell including a nanotube. The device includes a vertical transistor and a capacitor cell both using a single nanotube to form the individual devices.

Abstract: A stereolithographic (STL) apparatus for forming structures such as semiconductor die packages which uses a laser beam focused to a generally annular “spot” having an annulus of enhanced laser power surrounding a central “hole” of reduced (or no) laser power. The structures are formed of a stack of light-polymerized photopolymer layers. Scanning of a beam having power concentrated in the annulus enables simultaneous production of a self-supporting structure having at least semisolid, smooth lateral outer polymer walls and an upper hardened polymer skin extending over liquid polymer still lying between the walls. The structure may be subjected to heat or broad source light of suitable wavelength after removal from the STL apparatus to accelerate complete polymerization of the structure to a solid state.

Abstract: An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable bond pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable bond pads to one of the MCM's ground pins. By applying a supply voltage to the test mode enable bond pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a ground voltage applied to the test mode enable bond pads through the ground pins so the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging.

Abstract: An integrated circuit is provided with one or more connectors which allow an opto-electric device to be mounted on the integrated circuit directly on top of or underneath of it. Multiple opto-electric device interface regions can be defined on the integrated circuit such that an opto-electric device can be connected in a variety of directions or such that multiple opto-electric devices can be connected. In addition, an opto-electric device interface may be provided that causes the opto-electric device's leads to be directed to the corresponding integrated circuit lead in the shortest possible distance regardless of how the opto-electric device is positioned. Also disclosed is a substrate-mounted optical transmission system that may be used in connection with the opto-electric device.

Abstract: The formation of routing traces on an external surface of a semiconductor device, such as a flip-chip, which has a plurality of ball or bump sites patterned in specific locations, wherein the ball or bump sites are in electrical communication with external communication traces which are used to route signals from the flip-chip integrated circuitry. Such external communication traces generally result in unused space on the exterior surface of the flip-chip. This unused space can be utilized for forming routing traces to connect portions of the internal circuitry of the flip-chip rather than forming such routing traces internally, for forming routing traces to connect two or more semiconductor dice, or for forming routing traces for use as repair mechanisms.