Abstract: A circuit transfers data in an array of memory cells arranged in rows and columns. The circuit includes a plurality of row lines, a plurality of pairs of complementary digit lines, and an array of memory cells, each memory cell having a control terminal coupled to one of the row lines and a data terminal coupled to one of the complementary digit lines of one of the pairs of complementary digit lines responsive to a row enable signal on the row line of the row corresponding to the memory cell. A plurality of sense amplifiers are included in the circuit, each sense amplifier coupled to an associated pair of first and second complementary digit lines which senses a voltage differential between the first and second complementary digit lines and, in response to the sensed voltage differential, drives the first and second complementary digit lines to voltage levels corresponding to complementary logic states.

Abstract: A method for forming a semiconductor device comprises the steps of providing a semiconductor die having a plurality of pads thereon with at least one bond wire electrically coupled with one of the pads and providing a holder having a cavity therein. The die is placed in the cavity, then a layer of encapsulation is formed within the cavity to cover the die. Subsequently, the encapsulated die is removed from the cavity.

Abstract: A memory device has an open-array architecture that includes alternate digit lines in the end subarrays that are not normally coupled to a sense amplifier. These digit lines are not normally coupled to a sense amplifier because there is no adjacent subarray containing digit lines that could be coupled to the other input of the sense amplifier. A sense amplifier is provided for each of these normally unused digit lines, and each normally unused digit line is coupled to one of the imports of a respective sense amplifier. The other input of each sense amplifier is coupled to a dummy load that is provided to simulate the resistance and capacitance of an actual digit line. The dummy load has a capacitance that may be adjusted so that the capacitance at both inputs to each sense amplifier are substantially equal. As a result, normally unused digit lines in the end subarray of a memory array, as well as the memory cells coupled to the digit lines, may be used.

Abstract: The formation of routing traces on an external surface of a semiconductor device, such as a flip-chip, which has a plurality of ball or bump sites patterned in specific locations, wherein the ball or bump sites are in electrical communication with external communication traces which are used to route signals from the flip-chip integrated circuitry. Such external communication traces generally result in unused space on the exterior surface of the flip-chip. This unused space can be utilized for forming routing traces to connect portions of the internal circuitry of the flip-chip rather than forming such routing traces internally, for forming routing traces to connect two or more semiconductor dice, or for forming routing traces for use as repair mechanisms.

Abstract: An extensive network of N-channel transistor formed capacitor, with one node tie directly to Vcc power bus and the other node directly Vss power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 &mgr;F.

Abstract: The formation of routing traces on an external surface of a semiconductor device, such as a flip-chip, which has a plurality of ball or bump sites patterned in specific locations, wherein the ball or bump sites are in electrical communication with external communication traces which are used to route signals from the flip-chip integrated circuitry. Such external communication traces generally result in unused space on the exterior surface of the flip-chip. This unused space can be utilized for forming routing traces to connect portions of the internal circuitry of the flip-chip rather than forming such routing traces internally, for forming routing traces to connect two or more semiconductor dice, or for forming routing traces for use as repair mechanisms.

Abstract: Logic circuitry formed in street areas between adjacent fabricated electronic devices may be used as auxiliary or redundant components to salvage one or more otherwise defective devices. Logic circuitry is selectively coupled to the defective device(s) to directly replace or facilitate the replacement of defective components on one or more fabricated devices, thereby resulting in a single operable electronic device. The invention may be used to increase the production yield of electronic devices, particularly, semiconductor integrated circuits. The invention permits the fabrication of discretionary wiring during the normal metalization of semiconductor layers to interconnect electronic devices at the same time as the formation of the normal wiring/circuitry of the devices.

Abstract: A SIMM (single in-line memory module) board is provided with a plurality of integrated semiconductor memory or other integrated semiconductor circuit devices which include, as a part of each integrated circuit device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the device to the board. By connecting the on-chip capacitors of the integrated circuit devices in parallel, sufficient capacitance is provided to stabilize current to all of the integrated circuit devices.

Abstract: Logic circuitry formed in street areas between adjacent fabricated electronic devices may be used as auxiliary or redundant components to salvage one or more otherwise defective devices. Logic circuitry is selectively coupled to the defective device(s) to directly replace or facilitate the replacement of defective components on one or more fabricated devices, thereby resulting in a single operable electronic device. The invention may be used to increase the production yield of electronic devices, particularly, semiconductor integrated circuits. The invention permits the fabrication of discretionary wiring during the normal metalization of semiconductor layers to interconnect electronic devices at the same time as the formation of the normal wiring/circuitry of the devices.

Abstract: A heat sink is provided for use with stacks of integrated chips. The heat sink includes a thermally conductive body having a heat absorbing section which is inserted within the chip stack, and heat transfer and dissipating sections which are located outside of the chip stack.

Abstract: A circuit transfers data in an array of memory cells arranged in rows and columns. The circuit includes a plurality of row lines, a plurality of pairs of complementary digit lines, and an array of memory cells, each memory cell having a control terminal coupled to one of the row lines and a data terminal coupled to one of the complementary digit lines of one of the pairs of complementary digit lines responsive to a row enable signal on the row line of the row corresponding to the memory cell. A plurality of sense amplifiers are included in the circuit, each sense amplifier coupled to an associated pair of first and second complementary digit lines which senses a voltage differential between the first and second complementary digit lines and, in response to the sensed voltage differential, drives the first and second complementary digit lines to voltage levels corresponding to complementary logic states.

Abstract: An integrated circuit is provided with one or more connectors which allow an opto-electric device to be mounted on the integrated circuit directly on top of or underneath of it. Multiple opto-electric device interface regions can be defined on the integrated circuit such that an opto-electric device can be connected in a variety of directions or such that multiple opto-electric devices can be connected. In addition, a opto-electric device interface may be provided that causes the opto-electric device's leads to be directed to the corresponding integrated circuit lead in the shortest possible distance regardless of how the opto-electric device is positioned.

Abstract: An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable bond pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable bond pads to one of the MCM's ground pins. By applying a supply voltage to the test mode enable bond pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a ground voltage applied to the test mode enable bond pads through the ground pins so the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging.

Abstract: A heat sink is provided for use with stacks of integrated chips. The heat sink includes a thermally conductive body having a heat absorbing section which is inserted within the chip stack, and heat transfer and dissipating sections which are located outside of the chip stack.

Abstract: The provision of an isolation gate connecting unassociated active areas of adjacent transistors formed in a semiconductor substrate provides effective isolation of the adjacent transistors with no additional process steps required. The isolation gate is tied to a reference to ensure that a channel between the unassociated active areas is not formed, and effective isolation is provided. The adjacent transistors are cross coupled to form sense amplifiers for dynamic random access memory devices.

Abstract: An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable bond pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable bond pads to one of the MCM's ground pins. By applying a supply voltage to the test mode enable bond pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a ground voltage applied to the test mode enable bond pads through the ground pins so the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging.

Abstract: A circuit for reading and forcing a voltage at a node of an integrated circuit. In one embodiment, the circuit comprises a pass element that has an output that is coupled to a pin of the integrated circuit. A reset circuit is coupled to the pass circuit and is operable to activate and reset the pass circuit. Finally, a pass control circuit is coupled to provide a signal to the pass circuit that drives the pass circuit when active to pass the voltage at the node to the pin. In one embodiment, the circuit further includes a scaler circuit that establishes a ratio between the voltage at the node and the voltage at the pin such that high voltages can be passed to or from the node by the pass element.

Abstract: Methods for testing semiconductor memory devices are performed during the writing and reading of test information to and from memory cells. During the tests, operational parameters such as commencement of timing signals and the voltage levels thereof which are employed to activate components of a memory device are controllably adjusted in an effort to intentionally imbalance or alter the voltage differential appearing on the bit lines. If the memory device has a defect, the voltage levels on the bit lines are altered to such a degree that the sense amplifier, although properly sensing the voltage differential, incorrectly senses the intended test information stored in the memory cells. As the parameters are manipulated, the test information written from the memory cell and error signals are generated when the information is not the same. Circuitry for performing methods for testing semiconductor memory devices during the writing and reading of test information to and from memory cells is also disclosed.

Abstract: A heat sink is provided for use with stacks of integrated chips. The heat sink includes a thermally conductive body having a heat absorbing section which is inserted within the chip stack, and heat transfer and dissipating sections which are located outside of the chip stack.

Abstract: A heat sink is provided for use with stacks of integrated chips. The heat sink includes a thermally conductive body having a heat absorbing section which is inserted within the chip stack, and heat transfer and dissipating sections which are located outside of the chip stack.