Abstract: A method for producing a monolithic, seamless, polymeric housing structure for a micromachine uses a stereolithographic method to produce the structure layer by layer by exposing sequentially formed films of photopolymer to a beam of electromagnetic radiation scanned over patterns of locations corresponding to at least partially superimposed layers of the housing structure. The housing structure may include openings through which movable elements such as shafts and linkages may extend, and may provide sealed passage for electrical conductors therethrough from the micromachine to the exterior of the housing structure. Complex housing structures including closed or almost closed chambers and interior partition walls as well as interior passages of complex configuration may be formed to accommodate individual components or component assemblies.

Abstract: A stereolithographic method and apparatus for forming polymeric structures comprising a plurality of overlying layers, each layer formed by polymerizing a thin layer of liquid photopolymer on a prior layer. Crevices formed at the layer interfaces are filled by a stereolithographic method comprising lifting the multilayered structure from the liquid photopolymer, draining excess liquid therefrom, tilting the structure to provide an acute angle of incidence between an incident radiation beam and a side wall of the object, and applying radiation to the crevice to polymerize at least the surface of a quantity of liquid photopolymer therein. The structure may then be subjected to a separate final full cure to fully harden the structure. An exemplary use is the packaging of electronic components and the like.

Abstract: A stereolithographic (STL) apparatus for forming structures such as semiconductor die packages which uses a laser beam focused to a generally annular “spot” having an annulus of enhanced laser power surrounding a central “hole” of reduced (or no) laser power. The structures are formed of a stack of light-polymerized photopolymer layers. Scanning of a beam having power concentrated in the annulus enables simultaneous production of a self-supporting structure having at least semisolid, smooth lateral outer polymer walls and an upper hardened polymer skin extending over liquid polymer still lying between the walls. The structure may be subjected to heat or broad source light of suitable wavelength after removal from the STL apparatus to accelerate complete polymerization of the structure to a solid state.

Abstract: The formation of routing traces on an external surface of a semiconductor device, such as a flip-chip, which has a plurality of ball or bump sites patterned in specific locations, wherein the ball or bump sites are in electrical communication with external communication traces which are used to route signals from the flip-chip integrated circuitry. Such external communication traces generally result in unused space on the exterior surface of the flip-chip. This unused space can be utilized for forming routing traces to connect portions of the internal circuitry of the flip-chip rather than forming such routing traces internally, for forming routing traces to connect two or more semiconductor dice, or for forming routing traces for use as repair mechanisms.

Abstract: Logic circuitry formed in street areas between adjacent fabricated electronic devices may be used as auxiliary or redundant components to salvage one or more otherwise defective devices. Logic circuitry is selectively coupled to the defective device(s) to directly replace or facilitate the replacement of defective components on one or more fabricated devices, thereby resulting in a single operable electronic device. The invention may be used to increase the production yield of electronic devices, particularly, semiconductor integrated circuits. The invention permits the fabrication of discretionary wiring during the normal metalization of semiconductor layers to interconnect electronic devices at the same time as the formation of the normal wiring/circuitry of the devices.

Abstract: Logic circuitry formed in street areas between adjacent fabricated electronic devices may be used as auxiliary or redundant components to salvage one or more otherwise defective devices. Logic circuitry is selectively coupled to the defective device(s) to directly replace or facilitate the replacement of defective components on one or more fabricated devices, thereby resulting in a single operable electronic device. The invention may be used to increase the production yield of electronic devices, particularly, semiconductor integrated circuits. The invention permits the fabrication of discretionary wiring during the normal metalization of semiconductor layers to interconnect electronic devices at the same time as the formation of the normal wiring/circuitry of the devices.

Abstract: An integrated circuit is provided with one or more connectors which allow an opto-electric device to be mounted on the integrated circuit directly on top of or underneath of it. Multiple opto-electric device interface regions can be defined on the integrated circuit such that an opto-electric device can be connected in a variety of directions or such that multiple opto-electric devices can be connected. In addition, an opto-electric device interface may be provided that causes the opto-electric device's leads to be directed to the corresponding integrated circuit lead in the shortest possible distance regardless of how the opto-electric device is positioned.

Abstract: Provided herein are vertical nanotube semiconductor devices and methods for making the same. An embodiment of the semiconductor devices comprises a vertical transistor/capacitor cell including a nanotube. The device includes a vertical transistor and a capacitor cell both using a single nanotube to form the individual devices.

Abstract: A stereolithographic method and apparatus for forming polymeric structures comprising a plurality of overlying layers, each layer formed by polymerizing a thin layer of liquid photopolymer on a prior layer. Crevices formed at the layer interfaces are filled by a stereolithographic method comprising lifting the multilayered structure from the liquid photopolymer, draining excess liquid therefrom, tilting the structure to provide an acute angle of incidence between an incident radiation beam and a side wall of the object, and applying radiation to the crevice to polymerize at least the surface of a quantity of liquid photopolymer therein. The structure may then be subjected to a separate final full cure to fully harden the structure. An exemplary use is the packaging of electronic components and the like.

Abstract: A stereolithographic method and apparatus for forming polymeric structures comprising a plurality of overlying layers, each layer formed by polymerizing a thin layer of liquid photopolymer on a prior layer. Crevices formed at the layer interfaces are filled by a stereolithographic method comprising lifting the multilayered structure from the liquid photopolymer, draining excess liquid therefrom, tilting the structure to provide an acute angle of incidence between an incident radiation beam and a side wall of the object, and applying radiation to the crevice to polymerize at least the surface of a quantity of liquid photopolymer therein. The structure may then be subjected to a separate final full cure to fully harden the structure. An exemplary use is the packaging of electronic components and the like.

Abstract: A stereolithographic (STL) apparatus for forming structures such as semiconductor die packages which uses a laser beam focused to a generally annular “spot” having an annulus of enhanced laser power surrounding a central “hole” of reduced (or no) laser power. The structures are formed of a stack of light-polymerized photopolymer layers. Scanning of a beam having power concentrated in the annulus enables simultaneous production of a self-supporting structure having at least semisolid, smooth lateral outer polymer walls and an upper hardened polymer skin extending over liquid polymer still lying between the walls. The structure may be subjected to heat or broad source light of suitable wavelength after removal from the STL apparatus to accelerate complete polymerization of the structure to a solid state.

Abstract: A stereolithographic method and apparatus for forming polymeric structures comprising a plurality of overlying layers, each layer formed by polymerizing a thin layer of liquid photopolymer on a prior layer. Crevices formed at the layer interfaces are filled by a stereolithographic method comprising lifting the multilayered structure from the liquid photopolymer, draining excess liquid therefrom, tilting the structure to provide an acute angle of incidence between an incident radiation beam and a side wall of the object, and applying radiation to the crevice to polymerize at least the surface of a quantity of liquid photopolymer therein. The structure may then be subjected to a separate final full cure to fully harden the structure. An exemplary use is the packaging of electronic components and the like.

Abstract: A heat sink is provided for use with stacks of integrated chips. The heat sink includes a thermally conductive body having a heat absorbing section which is inserted within the chip stack, and heat transfer and dissipating sections which are located outside of the chip stack.

Abstract: A stereolithographic method and apparatus for forming polymeric structures comprising a plurality of overlying layers, each layer formed by polymerizing a thin layer of liquid photopolymer on a prior layer. Crevices formed at the layer interfaces are filled by a stereolithographic method comprising lifting the multilayered structure from the liquid photopolymer, draining excess liquid therefrom, tilting the structure to provide an acute angle of incidence between an incident radiation beam and a side wall of the object, and applying radiation to the crevice to polymerize at least the surface of a quantity of liquid photopolymer therein. The structure may then be subjected to a separate final full cure to fully harden the structure. An exemplary use is the packaging of electronic components and the like.

Abstract: Adjacent unassociated field-effect transistors are formed from a single continuous layer of uniformly doped material in a semiconductor substrate. An insulating layer is formed over the active layer. A number of gates in a conductive layer define the transistors. Forming a connection between one of the gates and a reference potential forms a boundary between the unassociated transistors across the active material by preventing carrier transport thereacross.

Abstract: The formation of routing traces on an external surface of a semiconductor device, such as a flip-chip, which has a plurality of ball or bump sites patterned in specific locations, wherein the ball or bump sites are in electrical communication with external communication traces which are used to route signals from the flip-chip integrated circuitry. Such external communication traces generally result in unused space on the exterior surface of the flip-chip. This unused space can be utilized for forming routing traces to connect portions of the internal circuitry of the flip-chip rather than forming such routing traces internally, for forming routing traces to connect two or more semiconductor dice, or for forming routing traces for use as repair mechanisms.

Abstract: A heat sink is provided for use with stacks of integrated chips. The heat sink includes a thermally conductive body having a heat absorbing section which is inserted within the chip stack, and heat transfer and dissipating sections which are located outside of the chip stack.

Abstract: An extensive network of N-channel transistor formed capacitor, with one node tie directly to VCC power bus and the other node directly VSS power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 &mgr;F.

Abstract: A circuit board has traces attached to a flexible trace surface such that the traces can be displaced in a direction of thermal expansion of a component attached to the traces without causing the failure of the solder joint between the component and the trace. In one embodiment, the printed circuit board substrate is etched away in areas not covered by the traces such that flexible protuberances are formed from the substrate underneath the traces. In one method for constructing such a circuit board, a conductive layer is deposited on the printed circuit board substrate. The conductive layer is then etched to form conductive traces. The printed circuit board substrate is then selectively etched using the traces as a mask for etching the printed circuit board substrate. In a second printed circuit board embodiment, a flexible layer of a material is deposited onto the printed circuit board substrate. The traces are then formed on top of the flexible layer.

Abstract: An integrated circuit is provided with one or more connectors which allow an opto-electric device to be mounted on the integrated circuit directly on top of or underneath of it. Multiple opto-electric device interface regions can be defined on the integrated circuit such that an opto-electric device can be connected in a variety of directions or such that multiple opto-electric devices can be connected. In addition, an opto-electric device interface may be provided that causes the opto-electric device's leads to be directed to the corresponding integrated circuit lead in the shortest possible distance regardless of how the opto-electric device is positioned.