Patents by Inventor Kevin L. Lin

Kevin L. Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12107044
    Abstract: Embodiments include a substrate and a method of forming the substrate. A substrate includes an interlayer dielectric and conductive traces in the interlayer dielectric (ILD). The conductive traces may include a first conductive trace surrounded by a second and third conductive traces. The substrate also includes a photoresist block in a region of the ILD. The region may be directly surrounded by the ILD and first conductive trace, and the photoresist block may be between the first conductive trace. The photoresist block may have a top surface that is substantially coplanar to top surfaces of the ILD and conductive traces. The photoresist block may have a width substantially equal to a width of the conductive traces. The photoresist block may be in the first conductive trace and between the second and third conductive traces. The photoresist block may include a metal oxide core embedded with organic ligands.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: October 1, 2024
    Assignee: Intel Corporation
    Inventors: Marie Krysak, Kevin L. Lin, Robert Bristol, Charles H. Wallace
  • Publication number: 20240304549
    Abstract: Integrated circuit metallization lines having a planar top surface but different vertical heights, for example to control intra-layer resistance/capacitance of integrated circuit interconnect. A hardmask material layer may be inserted between two thicknesses of dielectric material that are over a via metallization. Following deposition of the hardmask material layer, trench openings may be patterned through the hardmask layer to define where line metallization will have a greater height. Following the deposition of a thickness of dielectric material over the hardmask material layer, a trench pattern may be etched through the uppermost thickness of dielectric material, exposing the hardmask material layer wherever the trench does not coincide with an opening in the hardmask material layer. The trench etch may be retarded where the hardmask material layer is exposed, resulting to trenches of differing depth. Trenches of differing depth may be filled with metallization and then planarized.
    Type: Application
    Filed: May 17, 2024
    Publication date: September 12, 2024
    Applicant: Intel Corporation
    Inventors: Hui Jae Yoo, Kevin L. Lin
  • Publication number: 20240243052
    Abstract: An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines.
    Type: Application
    Filed: March 29, 2024
    Publication date: July 18, 2024
    Applicant: Intel Corporation
    Inventors: Kevin L. Lin, Sukru Yemenicioglu, Patrick Morrow, Richard Schenker, Mauro Kobrinsky
  • Patent number: 12002754
    Abstract: Integrated circuit metallization lines having a planar top surface but different vertical heights, for example to control intra-layer resistance/capacitance of integrated circuit interconnect. A hardmask material layer may be inserted between two thicknesses of dielectric material that are over a via metallization. Following deposition of the hardmask material layer, trench openings may be patterned through the hardmask layer to define where line metallization will have a greater height. Following the deposition of a thickness of dielectric material over the hardmask material layer, a trench pattern may be etched through the uppermost thickness of dielectric material, exposing the hardmask material layer wherever the trench does not coincide with an opening in the hardmask material layer. The trench etch may be retarded where the hardmask material layer is exposed, resulting to trenches of differing depth. Trenches of differing depth may be filled with metallization and then planarized.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: June 4, 2024
    Assignee: Intel Corporation
    Inventors: Hui Jae Yoo, Kevin L. Lin
  • Patent number: 11990403
    Abstract: Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate. A plurality of alternating first and second conductive line types is disposed along a same direction of a back end of line (BEOL) metallization layer disposed in an inter-layer dielectric (ILD) layer disposed above the substrate. A dielectric layer is disposed on an uppermost surface of the first conductive line types but not along sidewalls of the first conductive line types, and is disposed along sidewalls of the second conductive line types but not on an uppermost surface of the second conductive line types.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: May 21, 2024
    Assignee: Intel Corporation
    Inventors: Kevin L. Lin, Richard E. Schenker, Jeffery D. Bielefeld, Rami Hourani, Manish Chandhok
  • Patent number: 11955377
    Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Kevin L. Lin, Robert L Bristol, James M. Blackwell, Rami Hourani, Marie Krysak
  • Patent number: 11953826
    Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: James M. Blackwell, Robert L. Bristol, Marie Krysak, Florian Gstrein, Eungnak Han, Kevin L. Lin, Rami Hourani, Shane M. Harlson
  • Patent number: 11948874
    Abstract: An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Kevin L. Lin, Sukru Yemenicioglu, Patrick Morrow, Richard Schenker, Mauro Kobrinsky
  • Publication number: 20240071917
    Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
    Type: Application
    Filed: October 27, 2023
    Publication date: February 29, 2024
    Inventors: Richard E. SCHENKER, Robert L. BRISTOL, Kevin L. LIN, Florian GSTREIN, James M. BLACKWELL, Marie KRYSAK, Manish CHANDHOK, Paul A. NYHUS, Charles H. WALLACE, Curtis W. WARD, Swaminathan SIVAKUMAR, Elliot N. TAN
  • Patent number: 11854787
    Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: December 26, 2023
    Assignee: Intel Corporation
    Inventors: Richard E. Schenker, Robert L. Bristol, Kevin L. Lin, Florian Gstrein, James M. Blackwell, Marie Krysak, Manish Chandhok, Paul A. Nyhus, Charles H. Wallace, Curtis W. Ward, Swaminathan Sivakumar, Elliot N. Tan
  • Patent number: 11784121
    Abstract: Disclosed herein are integrated circuit (IC) components with dummy structures, as well as related methods and devices. For example, in some embodiments, an IC component may include a dummy structure in a metallization stack. The dummy structure may include a dummy material having a higher Young's modulus than an interlayer dielectric of the metallization stack.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: October 10, 2023
    Assignee: Intel Corporation
    Inventors: Kevin L. Lin, Nicholas James Harold McKubre, Richard Farrington Vreeland, Sansaptak Dasgupta
  • Patent number: 11769814
    Abstract: A device is disclosed. The device includes a gate conductor, a first source-drain region and a second source-drain region. The device includes a first air gap space between the first source-drain region and a first side of the gate conductor and a second air gap space between the second source-drain region and a second side of the gate conductor. A hard mask layer that includes holes is under the gate conductor, the first source-drain region, the second source-drain region and the air gap spaces. A planar dielectric layer is under the hard mask.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: September 26, 2023
    Assignee: Intel Corporation
    Inventors: Ehren Mannebach, Aaron Lilak, Hui Jae Yoo, Patrick Morrow, Kevin L. Lin, Tristan Tronic
  • Publication number: 20230230919
    Abstract: An integrated circuit device includes a first interconnect layer, and a conductive first interconnect feature and a conductive second interconnect feature laterally separated by a body of insulating or semiconductor material. In an example, the first and second interconnect features are above the first interconnect layer. The integrated circuit device further includes a non-conductive feature above and on the first interconnect feature, and a conductive third interconnect feature above and on the second interconnect feature. The integrated circuit device also includes a second interconnect layer above the non-conductive feature and third interconnect features. In an example, the second and third interconnect features conductively couple the first and second interconnect layers.
    Type: Application
    Filed: January 19, 2022
    Publication date: July 20, 2023
    Applicant: Intel Corporation
    Inventors: Nafees A. Kabir, Kevin L. Lin
  • Patent number: 11670588
    Abstract: Integrated circuits including selectable vias are disclosed. The techniques are particularly well-suited to back end of line (BEOL) processes. In accordance with some embodiments, a selectable via includes a vertically-oriented thin film transistor structure having a wrap around gate, which can be used to effectively select (or deselect) the selectable via ad hoc. When a selectable via is selected, a signal is allowed to pass through the selectable via. Conversely, when the selectable via is not selected, a signal is not allowed to pass through the selectable via. The selectable characteristic of the selectable via allows multiple vias to share a global interconnect. The global interconnect can be connected to any number of selectable vias, as well as standard vias.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: June 6, 2023
    Assignee: Intel Corporation
    Inventors: Christopher Jezewski, Ashish Agrawal, Kevin L. Lin, Abhishek Sharma, Carl Naylor, Urusa Alaan
  • Patent number: 11626451
    Abstract: A magnetic memory device comprising a plurality of memory cells is disclosed. The memory device includes an array of memory cells where each memory cell includes a first material layer having a ferromagnetic material, a second material layer having ruthenium, and a third material layer having bismuth and/or antimony. The second material layer is sandwiched between the first material layer and the third material in a stacked configuration.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: April 11, 2023
    Assignee: Intel Corporation
    Inventors: Emily Walker, Carl H. Naylor, Kaan Oguz, Kevin L. Lin, Tanay Gosavi, Christopher J. Jezewski, Chia-Ching Lin, Benjamin W. Buford, Dmitri E. Nikonov, John J. Plombon, Ian A. Young, Noriyuki Sato
  • Patent number: 11616014
    Abstract: Disclosed herein are peripheral inductors for integrated circuits (ICs), as well as related methods and devices. In some embodiments, an IC device may include a die having an inductor extending around at least a portion of a periphery of the die.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: March 28, 2023
    Assignee: Intel Corporation
    Inventors: Kevin L. Lin, Paul B. Fischer
  • Publication number: 20230091603
    Abstract: Techniques are provided for forming one or more thermoelectric devices integrated within a substrate of an integrated circuit. Backside substrate processing may be used to form adjacent portions of the substrate that are doped with alternating dopant types (e.g., n-type dopants alternating with p-type dopants). The substrate can then be etched to form pillars of the various n-type and p-type portions. Adjacent pillars of opposite dopant type can be electrically connected together via a conductive layer. Additionally, the top portions of adjacent pillars are connected together, and the bottom portions of a next pair of adjacent pillars being coupled together, in a repeating pattern to ensure that current flows through the length of each of the doped pillars. The flow of current through alternating n-type and p-type doped material creates a heat flux that transfers heat from one end of the integrated thermoelectric device to the other end.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Applicant: INTEL CORPORATION
    Inventors: Noriyuki Sato, Hui Jae Yoo, Kevin L. Lin, Van H. Le, Abhishek Anil Sharma
  • Patent number: 11594485
    Abstract: An integrated circuit includes a base comprising an insulating dielectric. A plurality of conductive lines extends vertically above the base in a spaced-apart arrangement, the plurality including a first conductive line and a second conductive line adjacent to the first conductive line. A void is between the first and second conductive lines. A cap of insulating material is located above the void and defines an upper boundary of the void such that the void is further located between the base and the cap of insulating material. In some embodiments, one or more vias contacts an upper end of one or more of the conductive lines.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: February 28, 2023
    Assignee: Intel Corporation
    Inventors: Kevin L. Lin, Scott B. Clendenning, Tristan A. Tronic, Urusa Alaan, Ehren Mannebach
  • Patent number: 11462469
    Abstract: Techniques are disclosed that enable independent control of interconnect lines and line end structures using a single mask. The techniques provided are particularly useful, for instance, where single mask lithography processes limit the scaling of line end structures. In some embodiments, the techniques can be implemented using a liner body and multiple angled etches of the liner body to provide a line end structure comprised of a remaining portion of the liner body. In such cases, the line end structure material enables an etch rate that is slower than the etch rate of surrounding insulator materials. Furthermore, the line end structure can be of minimal size not attainable using conventional single mask processes. In other embodiments, the techniques can be implemented using a hardmask that includes hardmask features defining lines, and one or more angled etches of the hardmask to provide line end structure(s) of minimal size.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: October 4, 2022
    Assignee: Intel Corporation
    Inventors: Kevin L. Lin, Nafees A. Kabir, Richard Schenker
  • Publication number: 20220262722
    Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
    Type: Application
    Filed: May 2, 2022
    Publication date: August 18, 2022
    Inventors: Richard E. SCHENKER, Robert L. BRISTOL, Kevin L. LIN, Florian GSTREIN, James M. BLACKWELL, Marie KRYSAK, Manish CHANDHOK, Paul A. NYHUS, Charles H. WALLACE, Curtis W. WARD, Swaminathan SIVAKUMAR, Elliot N. TAN