Patents by Inventor Ki-Tae Park

Ki-Tae Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD COMPENSATION OPERATING VOLTAGE, FLASH MEMORY DEVICE, AND DATA STORAGE DEVICE
    Publication number: 20120134213
    Abstract: Disclosed is a method generating a compensated operating voltage, such as a read voltage, in a non-volatile memory device, and a related non-volatile memory device. The operating voltage is compensated in response to one or more memory cell conditions such as temperature variation, programmed data state or physical location of a selected memory cell, page information for selected memory cell, or the location of a selected word line.
    Type: Application
    Filed: September 19, 2011
    Publication date: May 31, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoon Hee Choi, Ki Tae Park, Bo Geun Kim
  • Multilayered nonvolatile memory with adaptive control
    Patent number: 8144517
    Abstract: A method and device for adaptive control of multilayered nonvolatile semiconductor memory are provided, the device including memory cells organized into groups and a control circuit having a look-up matrix for providing control parameters for each of the groups, where characteristics of each group are stored in the look-up matrix, and the control parameters for each group are responsive to the stored characteristics for that group; the method including organizing memory cells into groups, storing characteristics for each group in a look-up matrix, providing control parameters for each of the groups, where the control parameters for each group are responsive to its stored characteristics, and driving each memory cell in accordance with its provided control parameters.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: March 27, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doo Gon Kim, Ki Tae Park, Myoung Gon Kang
  • Non-volatile memory system and programming method of the same
    Patent number: 8139406
    Abstract: A programming method for a non-volatile memory system includes storing multi-page program data and buffering the multi-page program data from a page buffer to a memory block and programming the multi-page program data through a predetermined number of program operations. The programming the multi-page program data includes programming memory cells of the memory block using a first threshold voltage lower than a desired threshold voltage based on the multi-page program data sequentially buffered by the page buffer in units of pages and programming the memory cells using the desired threshold voltage by increasing a threshold voltage of the memory cells by a predetermined level at each successive program operation.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: March 20, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki Tae Park, Yeong Taek Lee
  • MULTI-BIT FLASH MEMORY DEVICE AND MEMORY CELL ARRAY
    Publication number: 20120039122
    Abstract: A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2n pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits.
    Type: Application
    Filed: October 24, 2011
    Publication date: February 16, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-Tae PARK, Ki-Nam KIM, Yeong-Taek LEE
  • Programming method for non-volatile memory device
    Patent number: 8116131
    Abstract: Provided is a method of programming a non-volatile memory device. The method includes applying a first programming pulse to a corresponding wordline of the non-volatile memory device, applying a second programming pulse to the wordline, wherein a voltage of the second programming pulse is different from that of the first programming pulse, and applying voltages to each bitline connected to the wordline, the voltages applied to each of the bitlines are different from each other according to a plurality of bit values to be programmed to corresponding memory cells in response to the first programming pulse or the second programming pulse.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: February 14, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-tae Park, Yeong-taek Lee
  • 3-level non-volatile semiconductor memory device and method of driving the same
    Patent number: 8085607
    Abstract: A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: December 27, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Tae Park, Jung-Dal Choi, Sung-Kyu Jo
  • METHOD OF MERGING BLOCKS IN A SEMICONDUCTOR MEMORY DEVICE, AND SEMICONDUCTOR MEMORY DEVICE TO PERFORM A METHOD OF MERGING BLOCKS
    Publication number: 20110296087
    Abstract: In a method of merging blocks in a semiconductor memory device according to example embodiments, a plurality of data are written into one or more first blocks using a first program method. One or more merge target blocks that are required to be merged are selected among the one or more first blocks. A merge-performing block for a block merge operation is selected among the one or more first blocks and one or more second blocks. A plurality of merge target data are written from the merge target blocks into the merge-performing block using a second program method that is different from the first program method.
    Type: Application
    Filed: May 24, 2011
    Publication date: December 1, 2011
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Min-Seok Kim, Ki-Tae Park
  • NONVOLATILE MEMORY DEVICE, SYSTEM COMPRISING NONVOLATILE MEMORY DEVICE, AND READ OPERATION OF NONVOLATILE MEMORY DEVICE
    Publication number: 20110280070
    Abstract: A nonvolatile memory device comprises a memory cell array, a page buffer, and a control circuit. The memory cell array comprises multi-level cells configured to store hard decision data bits. The page buffer is configured to sense whether each of the multi-level cells assumes an on-cell state or an off-cell state in response to a first read voltage applied to a selected wordline during a first read operation, to set first soft decision data bits according to the first read operation, and to sense one or more hard decision data bits from each of the multi-level cells in response to a second read voltage applied to the selected wordline in a second read operation. The control circuit is configured to control the first read operation and the second read operation to be performed in succession.
    Type: Application
    Filed: March 28, 2011
    Publication date: November 17, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Young KIM, Ki Tae PARK, Bo Geun KIM
  • SEMICONDUCTOR DEVICE HAVING A FIELD EFFECT SOURCE/DRAIN REGION
    Publication number: 20110280066
    Abstract: A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by a fringe field of the gate. The other source/drain region is a PN-junction source/drain region having different impurity fields and different conductivity than the substrate. At least one of the source/drain regions is a field effect source/drain region. Accordingly, a short channel effect is reduced or eliminated in the device.
    Type: Application
    Filed: July 28, 2011
    Publication date: November 17, 2011
    Inventors: Ki-Tae Park, Jung-Dal Choi, Uk-Jin Roh
  • Multi-bit flash memory device and memory cell array
    Patent number: 8050089
    Abstract: A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2n pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: November 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Tae Park, Ki-Nam Kim, Yeong-Taek Lee
  • Nonvolatile memory device and program method with improved pass voltage window
    Patent number: 8045387
    Abstract: A flash memory and programming method are disclosed. The flash memory includes a memory cell array having memory cells arranged in a plurality of word lines including a selected word line and a plurality of non-selected word lines and a plurality of bit lines, a high voltage generator generating a program voltage applied to the selected word line, and a pass voltage applied to at least one of the non-selected word lines adjacent to the selected word line, and control logic controlling the generation of the program voltage, such that the program voltage is incrementally increased during a program operation, and generation of the pass voltage, such that the program voltage is incrementally increased.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: October 25, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Tae Park, Yeong-Taek Lee, Soon-Wook Hwang, Young-Wook Jeong
  • Semiconductor device having a field effect source/drain region
    Patent number: 8036031
    Abstract: A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by a fringe field of the gate. The other source/drain region is a PN-junction source/drain region having different impurity fields and different conductivity than the substrate. At least one of the source/drain regions is a field effect source/drain region. Accordingly, a short channel effect is reduced or eliminated in the device.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: October 11, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Tae Park, Jung-Dal Choi, Uk-Jin Roh
  • Semiconductor memory device with three-dimensional array and repair method thereof
    Patent number: 8031544
    Abstract: A nonvolatile memory device includes a three-dimensional (3D) cell array, a column selection circuit and a fuse block. The 3D cell array includes multiple cell arrays located in corresponding stacked substrate layers, the cell arrays sharing a bit line. The column selection circuit selects a memory unit included in the 3D cell array. The fuse block controls the column selection circuit to repair defective columns with one of multiple redundant bit lines located in the 3D cell array.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: October 4, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doo-Gon Kim, Ki-Tae Park
  • METHOD OF ERASING IN NON-VOLATILE MEMORY DEVICE
    Publication number: 20110235432
    Abstract: An erasing method of post-programming in a nonvolatile memory device. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are greater than or equal to a second voltage. The first voltage is different from the second voltage.
    Type: Application
    Filed: June 3, 2011
    Publication date: September 29, 2011
    Inventors: Doo-Gon Kim, Ki-Tae Park, Yeong-Taek Lee
  • Semiconductor memory device
    Patent number: 8027199
    Abstract: An electrically erasable programmable non-volatile semiconductor memory device. The semiconductor memory device includes a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells, a dummy memory cell, and a select gate transistor. Transfer transistors each having a current path connected between a corresponding wordline enable signal line and a corresponding wordline are controlled by an output of a block selection circuit. The transfer transistors include a dummy transfer transistor electrically coupled to the dummy memory cell, and configured to transmit a dummy wordline enable signal.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: September 27, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soon Wook Hwang, Ki Tae Park, Yeong Taek Lee
  • Nonvolatile memory device extracting parameters and nonvolatile memory system including the same
    Patent number: 8014201
    Abstract: The nonvolatile memory device includes a memory cell array having a plurality of memory blocks and a control logic circuit configured to store a parameter to access at least one of the plurality of memory blocks, configured to detect a variation of the parameter while accessing the at least one the memory block, and configured to store the varied parameter into the memory cell array in accordance with a result of the detection, wherein the control logic circuit is configured to utilize the varied parameter, which is stored in the memory cell array, while accessing the at least one memory block.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: September 6, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ki-Tae Park
  • Nonvolatile memory device, program method thereof, and memory system including the same
    Patent number: 8004898
    Abstract: A nonvolatile memory device may include a memory cell array adapted to store tail-bit flag information indicating tail-bit memory cells, and a tail-bit controller adapted to calibrate a program start voltage of normal memory cells and a program start voltage of the tail-bit memory cells independently based upon the tail-bit flag information.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: August 23, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Tae Park, Yeong-Taek Lee
  • FLASH MEMORY DEVICE USING ADAPTIVE PROGRAM VERIFICATION SCHEME AND RELATED METHOD OF OPERATION
    Publication number: 20110194346
    Abstract: A method of programming a flash memory device comprises programming selected memory cells, performing a verification operation to determine whether the selected memory cells have reached a target program state, and determining a start point of the verification operation based on a programming characteristic associated with a detection of a pass bit during programming of an initial program state.
    Type: Application
    Filed: December 9, 2010
    Publication date: August 11, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang Yong YOON, Ki Tae PARK, Moo Sung KIM, Bo Geun KIM, Hyun jun YOON
  • Flash memory devices that utilize age-based verify voltages to increase data reliability and methods of operating same
    Patent number: 7986560
    Abstract: Disclosed is a method of verifying a programmed condition of a flash memory device, being comprised of: determining a level of an additional verifying voltage in response to the number of programming/erasing cycles of memory cells; conducting a verifying operation to programmed memory cells with an initial verifying voltage lower than the additional verifying voltage; and selectively conducting an additional verifying operation with the additional verifying voltage to the program-verified memory cells in response to the number of programming/erasing cycles.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: July 26, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Tae Park, Yong-Seok Kim, Ki-Nam Kim, Yeong-Taek Lee
  • SEMICONDUCTOR MEMORY DEVICE INCLUDING PLURALITY OF MEMORY CHIPS
    Publication number: 20110164445
    Abstract: A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit.
    Type: Application
    Filed: March 21, 2011
    Publication date: July 7, 2011
    Inventor: Ki-Tae PARK