Abstract: A nonvolatile memory device comprises a memory cell array wherein a plurality of memory cell transistors are divided into multiple erase blocks. The multiple erase blocks are separated from each other by dummy word lines. During an erase operation of one of the multiple blocks, a dummy word line separating the one of the multiple blocks from other erase blocks is driven with a coupling inhibition voltage.

Abstract: An erasing method in a nonvolatile memory device is disclosed. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are greater than or equal to a second voltage. The first voltage is different from the second voltage, and the post-programming of the dummy memory cells comprises: applying a program voltage to a plurality of dummy word lines coupled to the dummy memory cells to post-program the dummy memory cells; and applying a pass voltage to a plurality of normal word lines coupled to the normal memory cells so that the normal memory cells are not post-programmed.

Abstract: A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.

Abstract: A method of programming a flash memory includes applying a shielding voltage to at least one shielding line, which is interposed between a plurality of wordlines and a selection line and operable to reduce capacitance-coupling between the wordline and the selection line during the programming operation, and applying a program voltage to memory cells through one of the wordlines.

Abstract: An electrically erasable programmable non-volatile semiconductor memory device. The semiconductor memory device includes a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells, a dummy memory cell, and a select gate transistor. Transfer transistors each having a current path connected between a corresponding wordline enable signal line and a corresponding wordline are controlled by an output of a block selection circuit. The transfer transistors include a dummy transfer transistor electrically coupled to the dummy memory cell, and configured to transmit a dummy wordline enable signal.

Abstract: A semiconductor memory device includes a first substrate having at least one string including a first select transistor, a second select transistor, and first memory cells connected in series between the first and second select transistors of the first substrate. The semiconductor memory device further includes a second substrate having at least one string including a first select transistor, a second select transistor, and second memory cells connected in series between the first and second select transistors of the second substrate. The number of the first memory cells of the at least one string of the first substrate is different from a number of the second memory cells of the at least one string of the second substrate. For example, the number of second memory cells may be less than the number of first memory cells.

Abstract: A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks each divided into a plurality of regions, and a control logic component. The control logic component selects a memory block to be programmed based on program/erase cycles of the memory blocks, and selects a program rule used to program the regions of the selected memory block.

Abstract: A semiconductor memory device for performing additional error correction code (ECC) correction according to a cell pattern and an electronic system including the same are provided. The semiconductor memory device includes a memory cell array configured to store user data; and an ECC engine configured to perform first ECC encoding on the user data, output a result of the first ECC encoding as ECC information, detect a predetermined cell pattern based on the user data, and additionally perform second ECC encoding on data of a cell corresponding to the predetermined cell pattern detected. Accordingly, data errors that may occur due to a certain cell pattern are prevented.

Abstract: A method of reading a flash memory device can include driving a selected word line by applying a selection voltage thereto and driving unselected word lines by applying a first voltage thereto, driving the unselected word lines and first and second selection lines by applying a second voltage that is higher than the first voltage thereto, and reading data from a memory cell that is coupled to the selected word line.

Abstract: An erasing method of post-programming in a nonvolatile memory device. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are greater than or equal to a second voltage. The first voltage is different from the second voltage.

Abstract: A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.

Abstract: A non volatile memory device and method of operating including providing a verification voltage to a gate of a selected memory cell within multiple memory cells and providing a first pass voltage to a gate of a non-selected memory cell within the memory cells during a program verification operation; and providing a read voltage to the gate of the selected memory cell and providing a second pass voltage to the gate of the non-selected memory cell during a read operation. The second pass voltage is greater than the first pass voltage.

Abstract: A method programming a non-volatile memory device using an incremental step pulse programming (ISPP) scheme is disclosed. The method includes operating in a first program mode during which a program pulse width is constant and a program voltage is successively increased per ISPP cycle, and during which a program operation and a verify operation are alternately repeated, and operating in a second program mode during which the program pulse width is successively increased per ISPP cycle and the program voltage is constant, and during which the program operation and the verify operation are alternately repeated, wherein operation in the second program mode follows operation in the first program mode only when the program voltage equals a maximum value, or when a verification result count value satisfies a predetermined condition.

Abstract: An electrically erasable programmable non-volatile semiconductor memory device. The semiconductor memory device includes a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells, a dummy memory cell, and a select gate transistor. Transfer transistors each having a current path connected between a corresponding wordline enable signal line and a corresponding wordline are controlled by an output of a block selection circuit. The transfer transistors include a dummy transfer transistor electrically coupled to the dummy memory cell, and configured to transmit a dummy wordline enable signal.

Abstract: This disclosure relates to a micro manipulator having a simple structure and having high possibility of recording a biological signal of a neuron at a desired position by improving positioning resolution of an electrode disposed adjacent to a subject's brain neuron or an electrode holder attached with the electrode. The micro manipulator according to the disclosure includes: a motor which includes a shaft and a vibration portion; a mobile which is connected to the shaft so as to be movable along the shaft; and a frame which supports the motor, wherein an electrode is connected to the mobile in a direction parallel to a longitudinal direction of the shaft, and wherein when the mobile moves linearly in accordance with a vibration of the shaft due to the vibration portion, the electrode moves linearly.

Abstract: A method of operating a memory device includes; defining a plurality of read levels, using the plurality of read levels to determine electrical property differences between first and second memory cells adjacent dispose along a common word line, and determining read data stored in the first and second memory cells in relation to the determination of electrical property differences between the first and second memory cells.

Abstract: The present invention relates to a delivery system for nucleic acid using a cationic polymer conjugate, and more specifically relates to a delivery system for nucleic acid comprising a cationic polymer conjugate prepared by conjugating hyaluronic acid or its derivative and polyethyleneimine, and a composition of delivering a nucleic acid into mammalian cell comprising a complex of the nucleic acid and a cationic polymer conjugate with electrostatic binding.

Abstract: Methods of programming nonvolatile memory devices include programming a plurality of nonvolatile multi-state memory cells in the non-volatile memory device with state-converted data derived from non-state-converted data. This state-converted data may be associated with a greater number of erased states relative to the non-state-converted data, when programmed into the plurality of nonvolatile memory cells. The methods also include generating a flag having a value that indicates which ones of the plurality of nonvolatile memory cells have been programmed with data that is swapped with data in other ones of the plurality of nonvolatile memory cells. This flag may also be programmed into the nonvolatile memory device. Operations may also be performed to read the state-converted data (and flag) from the plurality of nonvolatile memory cells and then decode the state-converted data into the non-state-converted data, based on the value of the flag.

Abstract: A read compensation circuit is provided. The read compensation circuit corrects a read error occurring in an erased cell based on a pattern of programmed cells adjacent to the erased cell. The read compensation circuit also transmit program state information of a memory cell stored in a page buffer to another page buffer through a bit line, thereby allowing page buffers to easily detect and correct errors occurring in memory cells.

Abstract: A nonvolatile memory device comprises a memory cell array wherein a plurality of memory cell transistors are divided into multiple erase blocks. The multiple erase blocks are separated from each other by dummy word lines. During an erase operation of one of the multiple blocks, a dummy word line separating the one of the multiple blocks from other erase blocks is driven with a coupling inhibition voltage.