Patents by Inventor Ki-Tae Park

Ki-Tae Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Flash memory devices that utilize age-based verify voltages to increase data reliability and methods of operating same
    Patent number: 7692970
    Abstract: Disclosed is a method of verifying a programmed condition of a flash memory device, being comprised of: determining a level of an additional verifying voltage in response to the number of programming/erasing cycles of memory cells; conducting a verifying operation to programmed memory cells with an initial verifying voltage lower than the additional verifying voltage; and selectively conducting an additional verifying operation with the additional verifying voltage to the program-verified memory cells in response to the number of programming/erasing cycles.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: April 6, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Tae Park, Yong-Seok Kim, Ki-Nam Kim, Yeong-Taek Lee
  • Semiconductor Device Having a Field Effect Source/Drain Region
    Publication number: 20100065894
    Abstract: A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by a fringe field of the gate. The other source/drain region is a PN-junction source/drain region having different impurity fields and different conductivity than the substrate. At least one of the source/drain regions is a field effect source/drain region. Accordingly, a short channel effect is reduced or eliminated in the device.
    Type: Application
    Filed: November 20, 2009
    Publication date: March 18, 2010
    Inventors: Ki-Tae Park, Jung-Dal Choi, Uk-Jin Roh
  • NONVOLATILE MEMORY DEVICE AND PROGRAM METHOD WITH IMPROVED PASS VOLTAGE WINDOW
    Publication number: 20100067305
    Abstract: A flash memory and programming method are disclosed. The flash memory includes a memory cell array having memory cells arranged in a plurality of word lines including a selected word line and a plurality of non-selected word lines and a plurality of bit lines, a high voltage generator generating a program voltage applied to the selected word line, and a pass voltage applied to at least one of the non-selected word lines adjacent to the selected word line, and control logic controlling the generation of the program voltage, such that the program voltage is incrementally increased during a program operation, and generation of the pass voltage, such that the program voltage is incrementally increased.
    Type: Application
    Filed: July 27, 2009
    Publication date: March 18, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ki-Tae PARK, Yeong-Taek LEE, Soon-Wook HWANG, Young-Wook JEONG
  • Nonvolatile memory device and driving method thereof
    Patent number: 7675783
    Abstract: Provided are a nonvolatile memory device and a driving method thereof. In the method of driving a nonvolatile memory device, a structural shape and position of a memory cell to be driven is determined, and then the memory cell is driven with an optimized operating condition according to a distribution of the memory cell using a determination result.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: March 9, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Tae Park, Ki-Nam Kim, Yeong-Taek Lee
  • Method of programming in a non-volatile memory device and non-volatile memory device for performing the same
    Patent number: 7672166
    Abstract: Provided are methods for programming in a non-volatile memory device, using incremental step pulses as a program voltage that is applied to a selected wordline. Methods may include applying a precharge voltage to an even bitline and an odd bitline such that the even bitline and the odd bitline are alternately charged with the precharge voltage and a boosted voltage that is higher than the precharge voltage. Methods may further include applying a bitline voltage corresponding to program data to a selected bitline of the even bitline and the odd bitline.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: March 2, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Tae Park, Yeong-Taek Lee, Ki-Nam Kim, Doo-Gon Kim
  • FLASH MEMORY DEVICE AND MEMORY SYSTEM
    Publication number: 20100046290
    Abstract: A flash memory device includes a first switch connecting one of a first cell string and a second cell string to a first bit line selectively, a second switch connecting the second cell string to a second bit line, and a control logic circuit providing bias voltages to the first and second cell strings through the first and second bit lines respectively and controlling the first and second cell stings to be simultaneously programmed.
    Type: Application
    Filed: July 27, 2009
    Publication date: February 25, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ki-Tae PARK, Myoung Gon KANG
  • Nonvolatile memory device extracting parameters and nonvolatile memory system including the same
    Publication number: 20100027337
    Abstract: The nonvolatile memory device includes a memory cell array having a plurality of memory blocks and a control logic circuit configured to store a parameter to access at least one of the plurality of memory blocks, configured to detect a variation of the parameter while accessing the at least one the memory block, and configured to store the varied parameter into the memory cell array in accordance with a result of the detection, wherein the control logic circuit is configured to utilize the varied parameter, which is stored in the memory cell array, while accessing the at least one memory block.
    Type: Application
    Filed: July 10, 2009
    Publication date: February 4, 2010
    Inventor: Ki-Tae Park
  • SEMICONDUCTOR MEMORY DEVICE INCLUDING PLURALITY OF MEMORY CHIPS
    Publication number: 20100027309
    Abstract: A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit.
    Type: Application
    Filed: January 27, 2009
    Publication date: February 4, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ki-Tae PARK
  • Nonvolatile memory device with NAND cell strings
    Patent number: 7652931
    Abstract: A nonvolatile memory device comprises a memory cell array wherein a plurality of memory cell transistors are divided into multiple erase blocks. The multiple erase blocks are separated from each other by dummy word lines. During an erase operation of one of the multiple blocks, a dummy word line separating the one of the multiple blocks from other erase blocks is driven with a coupling inhibition voltage.
    Type: Grant
    Filed: January 25, 2007
    Date of Patent: January 26, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Tae Park, Jung-Dal Choi
  • Flash memory device applying erase voltage
    Patent number: 7649775
    Abstract: A flash memory device includes; a plurality of layers, each one including memory cells arranged in a matrix of rows and columns, a layer decoder configured to select one of the plurality of layers to thereby define a selected layer and an unselected layer, a voltage generator configured to generate an erase voltage at a level higher than ground voltage, and an internal voltage, and a row select circuit configured to apply the erase voltage to the selected layer, and apply at least one of the erase voltage and the internal voltage to the unselected layer during an erase operation.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: January 19, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doo-Gon Kim, Ki-Tae Park
  • Flash Memory Devices that Utilize Age-Based Verify Voltages to Increase Data Reliability and Methods of Operating Same
    Publication number: 20100002523
    Abstract: Disclosed is a method of verifying a programmed condition of a flash memory device, being comprised of: determining a level of an additional verifying voltage in response to the number of programming/erasing cycles of memory cells; conducting a verifying operation to programmed memory cells with an initial verifying voltage lower than the additional verifying voltage; and selectively conducting an additional verifying operation with the additional verifying voltage to the program-verified memory cells in response to the number of programming/erasing cycles.
    Type: Application
    Filed: September 14, 2009
    Publication date: January 7, 2010
    Inventors: Ki-Tae Park, Yong-Seok Kim, Ki-Nam Kim, Yeong-Taek Lee
  • Non-volatile memory devices that utilize mirror-image programming techniques to inhibit program coupling noise and methods of programming same
    Patent number: 7639529
    Abstract: Non-volatile memory devices have improved data storage reliability resulting from mirror-image programming techniques that operate to reduce coupling noise between adjacent memory cells within a memory array. The adjacent memory cells include a first pair of memory cells and a second pair of memory cells. A program control circuit is provided to support mirror-image programming of the first and second pairs of memory cells when the two pairs of memory cells are storing the same 3-bit data.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: December 29, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki Tae Park, Jung Dal Choi
  • Memory device having multi-layer structure and driving method thereof
    Publication number: 20090307415
    Abstract: A memory device having a multi-layer structure, the memory device includes a first semiconductor layer including at least one memory cell array. The memory cell array includes a plurality of memory cells. A second semiconductor layer is on the first semiconductor layer. The second semiconductor layer includes a bit line and a page buffer connected to the bit line corresponding to the memory cell array. The memory device also includes a contact between the first semiconductor substrate and the second semiconductor substrate to connect the page buffer with the memory cell array.
    Type: Application
    Filed: June 4, 2009
    Publication date: December 10, 2009
    Inventors: Yong-Hoon Kang, Ki Tae Park
  • FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME
    Publication number: 20090290421
    Abstract: A flash memory device and a method of programming the same are disclosed. The flash memory device includes an array of memory cells intersected by a plurality of bit lines and a plurality of word lines. A page buffer circuit includes a plurality of latches coupled to an even virtual bit line and an odd virtual bitline. The page buffer circuit is configured to load data into the array of memory cells responsive to a select circuit, which is structured to electrically couple at least some of the bit lines to the plurality of latches of the page buffer circuit.
    Type: Application
    Filed: August 5, 2009
    Publication date: November 26, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ki-Tae PARK, Jung-Dal CHOI
  • Semiconductor device having a field effect source/drain region
    Patent number: 7623366
    Abstract: A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by a fringe field of the gate. The other source/drain region is a PN-junction source/drain region having different impurity fields and different conductivity than the substrate. At least one of the source/drain regions is a field effect source/drain region. Accordingly, a short channel effect is reduced or eliminated in the device.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: November 24, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Tae Park, Jung-Dal Choi, Uk-Jin Roh
  • MULTILAYERED NONVOLATILE MEMORY WITH ADAPTIVE CONTROL
    Publication number: 20090273977
    Abstract: A method and device for adaptive control of multilayered nonvolatile semiconductor memory are provided, the device including memory cells organized into groups and a control circuit having a look-up matrix for providing control parameters for each of the groups, where characteristics of each group are stored in the look-up matrix, and the control parameters for each group are responsive to the stored characteristics for that group; the method including organizing memory cells into groups, storing characteristics for each group in a look-up matrix, providing control parameters for each of the groups, where the control parameters for each group are responsive to its stored characteristics, and driving each memory cell in accordance with its provided control parameters.
    Type: Application
    Filed: May 26, 2009
    Publication date: November 5, 2009
    Inventors: Doo Gon Kim, Ki Tae Park, Myoung Gon Kang
  • MULTI-CHIP SEMICONDUCTOR DEVICE PROVIDING ENHANCED REDUNDANCY CAPABILITIES
    Publication number: 20090257297
    Abstract: A semiconductor device including a plurality of semiconductor chips is provided. A semiconductor device includes a storing unit in which redundancy information portions are stored, and a comparing unit comparing a current address to the redundancy information portions and enabling or disabling operation of a semiconductor device based on the comparison result.
    Type: Application
    Filed: March 12, 2009
    Publication date: October 15, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ki Tae PARK
  • MULTI-BIT FLASH MEMORY DEVICE AND MEMORY CELL ARRAY
    Publication number: 20090219758
    Abstract: A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2n pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits.
    Type: Application
    Filed: May 11, 2009
    Publication date: September 3, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-Tae PARK, Ki-Nam KIM, Yeong-Taek LEE
  • Flash memory device and method of programming the same
    Patent number: 7583540
    Abstract: A flash memory device and a method of programming the same are disclosed. The flash memory device includes an array of memory cells intersected by a plurality of bit lines and a plurality of word lines. A page buffer circuit includes a plurality of latches coupled to an even virtual bit line and an odd virtual bitline. The page buffer circuit is configured to load data into the array of memory cells responsive to a select circuit, which is structured to electrically couple at least some of the bit lines to the plurality of latches of the page buffer circuit.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: September 1, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Tae Park, Jung-Dal Choi
  • NON-VOLATILE MEMORY DEVICE ADAPTED TO REDUCE COUPLING EFFECT BETWEEN STORAGE ELEMENTS AND RELATED METHODS
    Publication number: 20090213661
    Abstract: A non-volatile semiconductor memory device comprises first and second sub-memory arrays and a strapping line disposed between the first and second sub-memory arrays. A programming operation of the first sub-memory array is performed by simultaneously applying a programming voltage to odd and even bit lines connected to memory cells within the first sub-memory array.
    Type: Application
    Filed: March 2, 2009
    Publication date: August 27, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-Tae PARK, Ki-Nam KIM, Yeong-Taek LEE