Patents by Inventor Ki-Tae Park

Ki-Tae Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • STACKED SEMICONDUCTOR APPARATUS, SYSTEM AND METHOD OF FABRICATION
    Publication number: 20130077374
    Abstract: A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.
    Type: Application
    Filed: October 24, 2012
    Publication date: March 28, 2013
    Inventors: Ki-Tae PARK, Kang-Wook LEE, Young-Don CHOI, Yun-Sang LEE
  • NONVOLATILE MEMORY DEVICE PROVIDING NEGATIVE VOLTAGE
    Publication number: 20130010539
    Abstract: Disclosed is a nonvolatile memory device which includes memory blocks, a pre-decoder, and a row decoder. Each of the memory blocks has a plurality of memory cells. The pre-decoder includes a multiplexer and negative level shifters. The multiplexer is configured to generate multiplexing signals in response to address signals. Each of the negative level shifters is configured to generate a converted multiplexing signal corresponding to a respective multiplexing signal by converting a multiplexing signal having a ground voltage into a converted multiplexing signal having a first negative voltage. The row decoder is configured to select at least one of the memory blocks in response to the converted multiplexing signals.
    Type: Application
    Filed: May 3, 2012
    Publication date: January 10, 2013
    Inventors: Sang-Won Shim, Pan-Suk Kwak, Ki-Tae Park, Yoon-Hee Choi
  • Nucleic acid delivery system comprising conjugates of PEI and hyaluronic acid
    Patent number: 8318856
    Abstract: The present invention relates to a delivery system for nucleic acid using a cationic polymer conjugate, and more specifically relates to a delivery system for nucleic acid comprising a cationic polymer conjugate prepared by conjugating hyaluronic acid or its derivative and polyethyleneimine, and a composition of delivering a nucleic acid into mammalian cell comprising a complex of the nucleic acid and a cationic polymer conjugate with electrostatic binding.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: November 27, 2012
    Assignees: Postech Academy-Industry Foundation, Korea University Industry and Academy Collaboration Foundation
    Inventors: Yu-Kyoung Oh, Hyun-Gu Kang, Ji-Seok Kim, Jiang Ge, Ki-Su Kim, Ki-Tae Park, Su-Eun Han, Ga-Yong Shim, Ii-Hwan Cho, Sei-Kwang Hahn
  • Method of erasing in non-volatile memory device
    Patent number: 8315105
    Abstract: An erasing method of post-programming in a nonvolatile memory device. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are greater than or equal to a second voltage. The first voltage is different from the second voltage.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: November 20, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doo-Gon Kim, Ki-Tae Park, Yeong-Taek Lee
  • Method of controlling a memory cell of non-volatile memory device
    Patent number: 8305816
    Abstract: A method of controlling data includes, with respect to non-volatile memory cells connected to bit lines corresponding to a first bit line group, first controlling data written to the non-volatile memory cells by varying a control voltage, and, with respect to non-volatile memory cells connected to bit lines corresponding to a second bit line group, second controlling data written to the non-volatile memory cells by varying a control voltage. The controlling may include reading or verifying. Before verification, the method may include writing data to the non-volatile memory cells.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: November 6, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-tae Park, Ki-nam Kim, Yeong-taek Lee
  • Nonvolatile memory device and related programming method
    Patent number: 8300463
    Abstract: A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks each divided into a plurality of regions, and a control logic component. The control logic component selects a memory block to be programmed based on program/erase cycles of the memory blocks, and selects a program rule used to program the regions of the selected memory block.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: October 30, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki Tae Park, Myoung Gon Kang
  • SEMICONDUCTOR MEMORY DEVICE INCLUDING PLURALITY OF MEMORY CHIPS
    Publication number: 20120262975
    Abstract: A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit.
    Type: Application
    Filed: June 29, 2012
    Publication date: October 18, 2012
    Inventor: Ki-Tae PARK
  • Semiconductor device having through electrode and method of fabricating the same
    Patent number: 8288278
    Abstract: A semiconductor device includes a substrate, and a through electrode passing through the substrate. The semiconductor device has a pad region and a through electrode region. A pad covers the pad region, extends into the through electrode region, and delimits an opening in the through electrode region. A through electrode extends through the semiconductor substrate below the hole in the pad in the through region.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: October 16, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Tae Park, Kang-Wook Lee, Hyun-Kyoung Kim
  • Flash memory device configured to reduce common source line noise, methods of operating same, and memory system incorporating same
    Patent number: 8264888
    Abstract: A flash memory device comprises memory cells connected between a bit line and a common source line, word lines connected to the memory cells, a common source line feedback circuit connected to a common source line (CSL) to detect the voltage level of the common source line, and a CSL feedback control logic configured to control a voltage level of a selected word line or a selected bit line to be compensated to a substantially constant value during a sensing operation of the memory cells based on the detected voltage level of the CSL.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: September 11, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-Hee Choi, Ki tae Park, Bo Geun Kim
  • Semiconductor device having a field effect source/drain region
    Patent number: 8259503
    Abstract: A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by a fringe field of the gate. The other source/drain region is a PN-junction source/drain region having different impurity fields and different conductivity than the substrate. At least one of the source/drain regions is a field effect source/drain region. Accordingly, a short channel effect is reduced or eliminated in the device.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: September 4, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Tae Park, Jung-Dal Choi, Uk-Jin Roh
  • Read compensation circuits and apparatus using same
    Patent number: 8243515
    Abstract: A read compensation circuit is provided. The read compensation circuit corrects a read error occurring in an erased cell based on a pattern of programmed cells adjacent to the erased cell. The read compensation circuit also transmit program state information of a memory cell stored in a page buffer to another page buffer through a bit line, thereby allowing page buffers to easily detect and correct errors occurring in memory cells.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: August 14, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ki Tae Park
  • NON-VOLATILE MEMORY, SYSTEM INCLUDING THE SAME, AND METHOD OF PROGRAMMING THE SAME
    Publication number: 20120203959
    Abstract: A method of programming a non-volatile memory that includes dumping first page data loaded to a cache latch to a first data latch and backing up the first page data to a second data latch.
    Type: Application
    Filed: February 9, 2012
    Publication date: August 9, 2012
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyun Jun Yoon, Ki Tae Park, Sang Yong Yoon, Seung-Hwan Shin
  • Method of programming nonvolatile memory device
    Patent number: 8238164
    Abstract: A method of programming a nonvolatile memory device comprises applying a gradually increasing program voltage to a memory cell, determining the number of verify voltages to be applied to the memory cell during a program loop based on the change of a threshold voltage from an initial state of the memory cell to a target state, and applying at least one of the determined verify voltages to the memory cell to verify whether the memory cell is programmed to the target state.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: August 7, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min Seok Kim, Jin Man Han, Ki Tae Park
  • CARRIER TAPE FOR TAB-PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20120186862
    Abstract: The present invention relates to a method for manufacturing a TAB tap. The method includes forming a circuit pattern region having input/output terminal pattern on a base film, and forming an exposing region at a convey region having a sprocket hole for exposing the base film. Accordingly, the present invention provides a TAB tape that improves reliability of a product by fundamentally preventing the generation of metal particles by forming exposing regions that expose a base film through selectively etching and removing a metal layer of a convey region formed at both side of a TAB tape and having a sprocket hole, and that prevents short-circuit by partially removing a base film at a predetermined region not having a circuit pattern formed thereon through etching.
    Type: Application
    Filed: July 22, 2011
    Publication date: July 26, 2012
    Applicant: LG Innotek Co., Ltd.
    Inventors: Tae Ki Hong, Han Mo Koo, Jun Young Lim, Ki Tae Park, Sang Ki Cho, Dae Sung Yoo
  • NAND flash memory device having dummy memory cells and methods of operating same
    Patent number: 8228738
    Abstract: A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: July 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Tae Park, Jung-Dal Choi, Jong-Sun Sel, Yoo-Cheol Shin
  • Semiconductor memory device including plurality of memory chips
    Patent number: 8213208
    Abstract: A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: July 3, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ki-Tae Park
  • PROGRAMMING METHOD FOR NON-VOLATILE MEMORY DEVICE
    Publication number: 20120140557
    Abstract: Provided is a method of programming a non-volatile memory device. The method includes applying a first programming pulse to a corresponding wordline of the non-volatile memory device, applying a second programming pulse to the wordline, wherein a voltage of the second programming pulse is different from that of the first programming pulse, and applying voltages to each bitline connected to the wordline, the voltages applied to each of the bitlines are different from each other according to a plurality of bit values to be programmed to corresponding memory cells in response to the first programming pulse or the second programming pulse.
    Type: Application
    Filed: February 14, 2012
    Publication date: June 7, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-tae PARK, Yeong-taek LEE
  • Memory device and operating method
    Patent number: 8194449
    Abstract: A method of operating a memory device includes; defining a plurality of read levels, using the plurality of read levels to determine electrical property differences between first and second memory cells adjacent dispose along a common word line, and determining read data stored in the first and second memory cells in relation to the determination of electrical property differences between the first and second memory cells.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: June 5, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ki Tae Park
  • Non-Volatile Memory Device And Read Method Thereof
    Publication number: 20120134207
    Abstract: In one embodiment, the method for reading memory cells in an array of non-volatile memory cells includes reading data from a memory cell using a set of hard decision voltages and at least a first set of soft decision voltages based on a single read command.
    Type: Application
    Filed: August 30, 2011
    Publication date: May 31, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangyong Yoon, Ki-tae Park, Hongrak Son
  • METHOD COMPENSATION OPERATING VOLTAGE, FLASH MEMORY DEVICE, AND DATA STORAGE DEVICE
    Publication number: 20120134213
    Abstract: Disclosed is a method generating a compensated operating voltage, such as a read voltage, in a non-volatile memory device, and a related non-volatile memory device. The operating voltage is compensated in response to one or more memory cell conditions such as temperature variation, programmed data state or physical location of a selected memory cell, page information for selected memory cell, or the location of a selected word line.
    Type: Application
    Filed: September 19, 2011
    Publication date: May 31, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoon Hee Choi, Ki Tae Park, Bo Geun Kim