Patents by Inventor Ki-yeon Park

Ki-yeon Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12135475
    Abstract: A display device includes a display layer emitting light. An infrared reflective layer is disposed on the display layer. An optical pattern is disposed on the infrared reflective layer. The optical pattern absorbs at least a portion of infrared light.
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: November 5, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hee Young Lee, Da Som Gu, Ki Jun Roh, Gil Yeong Park, Sung Guk An, So Yeon Han
  • Publication number: 20240338090
    Abstract: A display device including: a display unit including a plurality of sub-pixels; a touch sensing unit formed on the display unit and configured to sense a touch position; a code arrangement unit disposed on the touch sensing unit, wherein the code arrangement unit includes code patterns; and a surface protection cover disposed on the code arrangement unit, wherein a distance between the code patterns and a reflective surface formed below the code patterns is equal to or less than 55% of one width of one of the code patterns.
    Type: Application
    Filed: January 10, 2024
    Publication date: October 10, 2024
    Inventors: Da Som GU, Gil Yeong PARK, Ki Jun ROH, Sung Guk AN, Hee Young LEE, So Yeon HAN
  • Publication number: 20240309336
    Abstract: The present application relates to a method for producing a reassortant Reoviridae virus and a vector library for the same, and provides: a method for producing a reassortant Reoviridae virus by using a cell line into which an RNA polymerase is introduced and an expression vector library according to an aspect; a reassortant Reoviridae virus produced by the method; and an expression vector library for producing reassortant rotavirus.
    Type: Application
    Filed: June 24, 2022
    Publication date: September 19, 2024
    Inventors: Ki Weon SEO, Tae Woo KWON, Seo Yeon JUNG, Min Jung PARK, Kun Se LEE, Hyun Joo LEE
  • Patent number: 12089793
    Abstract: Disclosed are an autonomously traveling mobile robot and a traveling control method thereof, which can control the traveling of the mobile robot according to a first traveling mode in which the mobile robot travels by following obstacles located around the mobile robot or a second traveling mode in which the mobile robot travels in consideration of a positional relation with an existing traveling trajectory through which the mobile robot has already traveled, and generate candidate spots where the mobile robot can travel while the mobile robot travels along the traveling trajectory to implement a spiral cleaning pattern.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: September 17, 2024
    Assignee: YUJIN ROBOT CO., LTD.
    Inventors: Seong Ju Park, Gi Yeon Park, Ki San Hwang, Seung Ho Jang
  • Patent number: 12084665
    Abstract: The present invention relates to: acid-resistant yeast to which lactic acid productivity is imparted, and in which the conversion of pyruvate into acetaldehyde is inhibited and, consequently, the ethanol production pathway is inhibited; and a method for producing lactic acid by using same.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: September 10, 2024
    Assignee: SK Innovation Co., Ltd.
    Inventors: Jae Yeon Park, Tae Young Lee, Ki Sung Lee
  • Patent number: 10797160
    Abstract: A method of fabricating a semiconductor device may include forming a fin structure on a substrate; forming an interface film having a first thickness on the fin structure using a first process; forming a gate dielectric film having a second thickness on the interface film using a second process different from the first process; and densifying the gate dielectric film using a third process different from the first and second processes. The second thickness may be greater than the first thickness, and the first thickness of the interface film may be unchanged after the densifying of the gate dielectric film.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: October 6, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Jun Sim, Won-Oh Seo, Sun-Jung Kim, Ki-Yeon Park
  • Patent number: 10685957
    Abstract: A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgas sing prevention pattern sequentially stacked.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Hyun Choi, Yong-Suk Tak, Gi-Gwan Park, Bon-Young Koo, Ki-Yeon Park, Won-Oh Seo
  • Patent number: 10541127
    Abstract: A material layer, a semiconductor device including the material layer, and methods of forming the material layer and the semiconductor device are provided herein. A method of forming a SiOCN material layer may include supplying a silicon source onto a substrate, supplying a carbon source onto the substrate, supplying an oxygen source onto the substrate, supplying a nitrogen source onto the substrate, and supplying hydrogen onto the substrate. When a material layer is formed according to a method of the present inventive concepts, a material layer having a high tolerance to wet etching and/or good electric characteristics may be formed, and may even be formed when the method is performed at a low temperature.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: January 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-suk Tak, Gi-gwan Park, Jin-bum Kim, Bon-young Koo, Ki-yeon Park, Tae-jong Lee
  • Patent number: 10529555
    Abstract: A method of forming a SiOCN material layer, a material layer stack, a semiconductor device, a method of fabricating a semiconductor device, and a deposition apparatus, the method of forming a SiOCN material layer including providing a substrate; providing a silicon precursor onto the substrate; providing an oxygen reactant onto the substrate; providing a first carbon precursor onto the substrate; providing a second carbon precursor onto the substrate; and providing a nitrogen reactant onto the substrate, wherein the first carbon precursor and the second carbon precursor are different materials.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: January 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-suk Tak, Tae-jong Lee, Bon-young Koo, Ki-yeon Park, Sung-hyun Choi
  • Patent number: 10460927
    Abstract: A method of forming a SiOCN material layer, a material layer stack, a semiconductor device, a method of fabricating a semiconductor device, and a deposition apparatus, the method of forming a SiOCN material layer including providing a substrate; providing a silicon precursor onto the substrate; providing an oxygen reactant onto the substrate; providing a first carbon precursor onto the substrate; providing a second carbon precursor onto the substrate; and providing a nitrogen reactant onto the substrate, wherein the first carbon precursor and the second carbon precursor are different materials.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: October 29, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-suk Tak, Tae-jong Lee, Bon-young Koo, Ki-yeon Park, Sung-hyun Choi
  • Publication number: 20190287797
    Abstract: A method of forming a SiOCN material layer, a material layer stack, a semiconductor device, a method of fabricating a semiconductor device, and a deposition apparatus, the method of forming a SiOCN material layer including providing a substrate; providing a silicon precursor onto the substrate; providing an oxygen reactant onto the substrate; providing a first carbon precursor onto the substrate; providing a second carbon precursor onto the substrate; and providing a nitrogen reactant onto the substrate, wherein the first carbon precursor and the second carbon precursor are different materials.
    Type: Application
    Filed: May 24, 2019
    Publication date: September 19, 2019
    Inventors: Yong-suk TAK, Tae-jong LEE, Bon-young KOO, Ki-yeon PARK, Sung-hyun CHOI
  • Patent number: 10403739
    Abstract: A method for fabricating a semiconductor device includes forming a stacked structure including at least one sacrificial layer and at least one semiconductor layer alternately stacked on a substrate, forming a dummy gate structure on the stacked structure, etching a recess in the stacked structure using the dummy gate structure as a mask, etching portions of the sacrificial layer exposed by the recess to form an etched sacrificial layer, forming a first spacer film on the etched sacrificial layer, forming a second spacer film on the first spacer film, the second spacer film including a material different from a material of the first spacer film, removing a first portion of the second spacer film, such that a second portion of the second spacer film remains, and forming a third spacer film on the second portion of the second spacer film.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tea Won Kim, Yong Suk Tak, Ki Yeon Park
  • Publication number: 20190237563
    Abstract: A method of fabricating a semiconductor device may include forming a fin structure on a substrate; forming an interface film having a first thickness on the fin structure using a first process; forming a gate dielectric film having a second thickness on the interface film using a second process different from the first process; and densifying the gate dielectric film using a third process different from the first and second processes. The second thickness may be greater than the first thickness, and the first thickness of the interface film may be unchanged after the densifying of the gate dielectric film.
    Type: Application
    Filed: October 2, 2018
    Publication date: August 1, 2019
    Inventors: HYUN-JUN SIM, WON-OH SEO, SUN-JUNG KIM, KI-YEON PARK
  • Publication number: 20190006485
    Abstract: A method for fabricating a semiconductor device includes forming a stacked structure including at least one sacrificial layer and at least one semiconductor layer alternately stacked on a substrate, forming a dummy gate structure on the stacked structure, etching a recess in the stacked structure using the dummy gate structure as a mask, etching portions of the sacrificial layer exposed by the recess to form an etched sacrificial layer, forming a first spacer film on the etched sacrificial layer, forming a second spacer film on the first spacer film, the second spacer film including a material different from a material of the first spacer film, removing a first portion of the second spacer film, such that a second portion of the second spacer film remains, and forming a third spacer film on the second portion of the second spacer film.
    Type: Application
    Filed: January 9, 2018
    Publication date: January 3, 2019
    Inventors: Tea Won KIM, Yong Suk TAK, Ki Yeon PARK
  • Publication number: 20180301452
    Abstract: A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgas sing prevention pattern sequentially stacked.
    Type: Application
    Filed: June 12, 2018
    Publication date: October 18, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sung-Hyun Choi, Yong-Suk Tak, Gi-Gwan Park, Bon-Young Koo, Ki-Yeon Park, Won-Oh Seo
  • Patent number: 10096688
    Abstract: An integrated circuit device includes a fin type active area protruding from a substrate and having an upper surface at a first level; a nanosheet extending in parallel to the upper surface of the fin type active area and comprising a channel area, the nanosheet being located at a second level spaced apart from the upper surface of the fin type active area; a gate disposed on the fin type active area and surrounding at least a part of the nanosheet, the gate extending in a direction crossing the fin type active area; a gate dielectric layer disposed between the nanosheet and the gate; a source and drain region formed on the fin type active area and connected to one end of the nanosheet; a first insulating spacer on the nanosheet, the first insulating spacer covering sidewalls of the gate; and a second insulating spacer disposed between the gate and the source and drain region in a space between the upper surface of the fin type active area and the nanosheet, the second insulating spacer having a multilayer st
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: October 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-suk Tak, Gi-gwan Park, Tae-jong Lee, Bon-young Koo, Ki-yeon Park, Sung-hyun Choi
  • Patent number: 10026736
    Abstract: A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgassing prevention pattern sequentially stacked.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: July 17, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Hyun Choi, Yong-Suk Tak, Gi-Gwan Park, Bon-Young Koo, Ki-Yeon Park, Won-Oh Seo
  • Patent number: 9859393
    Abstract: A device includes: a gate line on an active region of a substrate, a pair of source/drain regions in the active region on both sides of the gate line, a contact plug on at least one source/drain region out of the pair of source/drain regions; and a multilayer-structured insulating spacer between the gate line and the contact plug. The multilayer-structured insulating spacer may include an oxide layer, a first carbon-containing insulating layer covering a first surface of the oxide layer adjacent to the gate line, and a second carbon-containing insulating layer covering a second surface of the oxide layer, opposite to the first surface of the oxide layer, adjacent to the contact plug.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: January 2, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-suk Tak, Tae-jong Lee, Hyun-seung Kim, Bon-young Koo, Ki-yeon Park, Gi-gwan Park, Mi-seon Park
  • Publication number: 20170317213
    Abstract: A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure directly on a sidewall of the gate structure, and a source/drain layer on a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a silicon oxycarbonitride (SiOCN) pattern and a silicon dioxide (SiO2) pattern sequentially stacked.
    Type: Application
    Filed: January 19, 2017
    Publication date: November 2, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Mi-Seon PARK, Gi-Gwan PARK, Tae-Jong LEE, Yong-Suk TAK, Ki-Yeon PARK
  • Publication number: 20170222014
    Abstract: A device includes: a gate line on an active region of a substrate, a pair of source/drain regions in the active region on both sides of the gate line, a contact plug on at least one source/drain region out of the pair of source/drain regions; and a multilayer-structured insulating spacer between the gate line and the contact plug. The multilayer-structured insulating spacer may include an oxide layer, a first carbon-containing insulating layer covering a first surface of the oxide layer adjacent to the gate line, and a second carbon-containing insulating layer covering a second surface of the oxide layer, opposite to the first surface of the oxide layer, adjacent to the contact plug.
    Type: Application
    Filed: January 9, 2017
    Publication date: August 3, 2017
    Inventors: Yong-suk Tak, Tae-jong Lee, Hyun-seung Kim, Bon-young Koo, Ki-yeon Park, Gi-gwan Park, Mi-seon Park