Patents by Inventor Ki-yeon Park
Ki-yeon Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240133519Abstract: A liquefied gas storage tank includes a corner block disposed on a corner portion, wherein the corner block includes a lower block, an upper block and an upper connecting block, the upper block includes a first inner fixing unit and a second inner fixing unit respectively provided inside a first surface and a second surface, bonded and connected to a secondary barrier, and each having a structure in which a primary inner plywood, a primary corner insulating material, and a primary outer plywood are stacked, and an inner bent portion installed at a corner spatial portion between the first inner fixing unit and the second inner fixing unit, and both side surfaces of the inner bent portion that are perpendicular to the secondary barrier each have a height reduced from a total height of each of the first and second inner fixing units.Type: ApplicationFiled: December 14, 2021Publication date: April 25, 2024Inventors: Won Seok HEO, Seong Bo PARK, Hye Min CHO, Ki Joong KIM, Cheon Jin PARK, Min Kyu PARK, Jung Kyu PARK, Byeong Jin JEONG, Dong Woo KIM, Sung Kyu HONG, Gwang Soo GO, Jee Yeon HEO
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Publication number: 20240084969Abstract: The liquefied gas storage tank includes a primary barrier, a primary insulation wall, a secondary barrier, and a secondary insulation wall. In a state where unit elements are arranged adjacent to each other, each of the unit elements being formed by stacking the secondary insulation wall, the secondary barrier, and a fixed insulation wall which is a part of the primary insulation wall, the primary insulation wall may comprise: a connection insulation wall provided in the space between the adjacent fixed insulation walls; first slits formed between the fixed insulation walls and the connection insulation wall when the connection insulation wall is inserted and installed between the adjacent fixed insulation walls; a plurality of second slits formed in a lengthwise direction and a widthwise direction of the fixed insulation walls; and a first insulating filler material for filling the first slits.Type: ApplicationFiled: December 15, 2021Publication date: March 14, 2024Inventors: Seong Bo PARK, Won Seok HEO, Hye Min CHO, Ki Joong KIM, Cheon Jin PARK, Min Kyu PARK, Jung Kyu PARK, Byeong Jin JEONG, Dong Woo KIM, Sung Kyu HONG, Gwang Soo GO, Jee Yeon HEO
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Publication number: 20240085948Abstract: A display device includes a display panel including a plurality of pixels, a folding area, a first non-folding area disposed on one side of the folding area, and a second non-folding area disposed on the other side of the folding area, a first adhesive layer disposed on one surface of the display panel, and a code pattern layer. The code pattern layer includes a light absorption layer disposed on one surface of the first adhesive layer, a base layer disposed on the light absorption layer, and a plurality of code patterns disposed on the base layer. A thickness of the base layer is smaller than a thickness of the first adhesive layer.Type: ApplicationFiled: April 5, 2023Publication date: March 14, 2024Inventors: So Yeon HAN, Hee Young LEE, Da Som GU, Ki Jun ROH, Gil Yeong PARK, Sung Guk AN
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Publication number: 20240067535Abstract: A water purifier includes: a filter module for providing purified water by filtering raw water; a fitting valve module detachably fastened to the filter module to provide at least one of a flow path for a flow of raw water supplied to the filter module and a flow path for a flow of the purified water discharged from the filter module; and a frame including a valve support for movably supporting the fitting valve module to be movable. The fitting valve module is selectively placed in a separated state in which the fitting valve module is separated from the filter module by moving in a direction away from the filter module, or a coupled state in which the fitting valve module coupled to the filter module by moving toward the filter module.Type: ApplicationFiled: December 30, 2021Publication date: February 29, 2024Applicant: COWAY CO., LTD.Inventors: Ki Hong MIN, Man Uk PARK, Yong Yeon NOH, Dae Hwan KIM, Doo Won HAN
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Patent number: 10797160Abstract: A method of fabricating a semiconductor device may include forming a fin structure on a substrate; forming an interface film having a first thickness on the fin structure using a first process; forming a gate dielectric film having a second thickness on the interface film using a second process different from the first process; and densifying the gate dielectric film using a third process different from the first and second processes. The second thickness may be greater than the first thickness, and the first thickness of the interface film may be unchanged after the densifying of the gate dielectric film.Type: GrantFiled: October 2, 2018Date of Patent: October 6, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Jun Sim, Won-Oh Seo, Sun-Jung Kim, Ki-Yeon Park
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Patent number: 10685957Abstract: A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgas sing prevention pattern sequentially stacked.Type: GrantFiled: June 12, 2018Date of Patent: June 16, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Hyun Choi, Yong-Suk Tak, Gi-Gwan Park, Bon-Young Koo, Ki-Yeon Park, Won-Oh Seo
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Patent number: 10541127Abstract: A material layer, a semiconductor device including the material layer, and methods of forming the material layer and the semiconductor device are provided herein. A method of forming a SiOCN material layer may include supplying a silicon source onto a substrate, supplying a carbon source onto the substrate, supplying an oxygen source onto the substrate, supplying a nitrogen source onto the substrate, and supplying hydrogen onto the substrate. When a material layer is formed according to a method of the present inventive concepts, a material layer having a high tolerance to wet etching and/or good electric characteristics may be formed, and may even be formed when the method is performed at a low temperature.Type: GrantFiled: October 28, 2016Date of Patent: January 21, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-suk Tak, Gi-gwan Park, Jin-bum Kim, Bon-young Koo, Ki-yeon Park, Tae-jong Lee
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Patent number: 10529555Abstract: A method of forming a SiOCN material layer, a material layer stack, a semiconductor device, a method of fabricating a semiconductor device, and a deposition apparatus, the method of forming a SiOCN material layer including providing a substrate; providing a silicon precursor onto the substrate; providing an oxygen reactant onto the substrate; providing a first carbon precursor onto the substrate; providing a second carbon precursor onto the substrate; and providing a nitrogen reactant onto the substrate, wherein the first carbon precursor and the second carbon precursor are different materials.Type: GrantFiled: May 24, 2019Date of Patent: January 7, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-suk Tak, Tae-jong Lee, Bon-young Koo, Ki-yeon Park, Sung-hyun Choi
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Patent number: 10460927Abstract: A method of forming a SiOCN material layer, a material layer stack, a semiconductor device, a method of fabricating a semiconductor device, and a deposition apparatus, the method of forming a SiOCN material layer including providing a substrate; providing a silicon precursor onto the substrate; providing an oxygen reactant onto the substrate; providing a first carbon precursor onto the substrate; providing a second carbon precursor onto the substrate; and providing a nitrogen reactant onto the substrate, wherein the first carbon precursor and the second carbon precursor are different materials.Type: GrantFiled: October 18, 2016Date of Patent: October 29, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-suk Tak, Tae-jong Lee, Bon-young Koo, Ki-yeon Park, Sung-hyun Choi
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Publication number: 20190287797Abstract: A method of forming a SiOCN material layer, a material layer stack, a semiconductor device, a method of fabricating a semiconductor device, and a deposition apparatus, the method of forming a SiOCN material layer including providing a substrate; providing a silicon precursor onto the substrate; providing an oxygen reactant onto the substrate; providing a first carbon precursor onto the substrate; providing a second carbon precursor onto the substrate; and providing a nitrogen reactant onto the substrate, wherein the first carbon precursor and the second carbon precursor are different materials.Type: ApplicationFiled: May 24, 2019Publication date: September 19, 2019Inventors: Yong-suk TAK, Tae-jong LEE, Bon-young KOO, Ki-yeon PARK, Sung-hyun CHOI
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Patent number: 10403739Abstract: A method for fabricating a semiconductor device includes forming a stacked structure including at least one sacrificial layer and at least one semiconductor layer alternately stacked on a substrate, forming a dummy gate structure on the stacked structure, etching a recess in the stacked structure using the dummy gate structure as a mask, etching portions of the sacrificial layer exposed by the recess to form an etched sacrificial layer, forming a first spacer film on the etched sacrificial layer, forming a second spacer film on the first spacer film, the second spacer film including a material different from a material of the first spacer film, removing a first portion of the second spacer film, such that a second portion of the second spacer film remains, and forming a third spacer film on the second portion of the second spacer film.Type: GrantFiled: January 9, 2018Date of Patent: September 3, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tea Won Kim, Yong Suk Tak, Ki Yeon Park
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Publication number: 20190237563Abstract: A method of fabricating a semiconductor device may include forming a fin structure on a substrate; forming an interface film having a first thickness on the fin structure using a first process; forming a gate dielectric film having a second thickness on the interface film using a second process different from the first process; and densifying the gate dielectric film using a third process different from the first and second processes. The second thickness may be greater than the first thickness, and the first thickness of the interface film may be unchanged after the densifying of the gate dielectric film.Type: ApplicationFiled: October 2, 2018Publication date: August 1, 2019Inventors: HYUN-JUN SIM, WON-OH SEO, SUN-JUNG KIM, KI-YEON PARK
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Publication number: 20190006485Abstract: A method for fabricating a semiconductor device includes forming a stacked structure including at least one sacrificial layer and at least one semiconductor layer alternately stacked on a substrate, forming a dummy gate structure on the stacked structure, etching a recess in the stacked structure using the dummy gate structure as a mask, etching portions of the sacrificial layer exposed by the recess to form an etched sacrificial layer, forming a first spacer film on the etched sacrificial layer, forming a second spacer film on the first spacer film, the second spacer film including a material different from a material of the first spacer film, removing a first portion of the second spacer film, such that a second portion of the second spacer film remains, and forming a third spacer film on the second portion of the second spacer film.Type: ApplicationFiled: January 9, 2018Publication date: January 3, 2019Inventors: Tea Won KIM, Yong Suk TAK, Ki Yeon PARK
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Publication number: 20180301452Abstract: A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgas sing prevention pattern sequentially stacked.Type: ApplicationFiled: June 12, 2018Publication date: October 18, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-Hyun Choi, Yong-Suk Tak, Gi-Gwan Park, Bon-Young Koo, Ki-Yeon Park, Won-Oh Seo
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Patent number: 10096688Abstract: An integrated circuit device includes a fin type active area protruding from a substrate and having an upper surface at a first level; a nanosheet extending in parallel to the upper surface of the fin type active area and comprising a channel area, the nanosheet being located at a second level spaced apart from the upper surface of the fin type active area; a gate disposed on the fin type active area and surrounding at least a part of the nanosheet, the gate extending in a direction crossing the fin type active area; a gate dielectric layer disposed between the nanosheet and the gate; a source and drain region formed on the fin type active area and connected to one end of the nanosheet; a first insulating spacer on the nanosheet, the first insulating spacer covering sidewalls of the gate; and a second insulating spacer disposed between the gate and the source and drain region in a space between the upper surface of the fin type active area and the nanosheet, the second insulating spacer having a multilayer stType: GrantFiled: July 11, 2016Date of Patent: October 9, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-suk Tak, Gi-gwan Park, Tae-jong Lee, Bon-young Koo, Ki-yeon Park, Sung-hyun Choi
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Patent number: 10026736Abstract: A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgassing prevention pattern sequentially stacked.Type: GrantFiled: December 20, 2016Date of Patent: July 17, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Hyun Choi, Yong-Suk Tak, Gi-Gwan Park, Bon-Young Koo, Ki-Yeon Park, Won-Oh Seo
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Patent number: 9859393Abstract: A device includes: a gate line on an active region of a substrate, a pair of source/drain regions in the active region on both sides of the gate line, a contact plug on at least one source/drain region out of the pair of source/drain regions; and a multilayer-structured insulating spacer between the gate line and the contact plug. The multilayer-structured insulating spacer may include an oxide layer, a first carbon-containing insulating layer covering a first surface of the oxide layer adjacent to the gate line, and a second carbon-containing insulating layer covering a second surface of the oxide layer, opposite to the first surface of the oxide layer, adjacent to the contact plug.Type: GrantFiled: January 9, 2017Date of Patent: January 2, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-suk Tak, Tae-jong Lee, Hyun-seung Kim, Bon-young Koo, Ki-yeon Park, Gi-gwan Park, Mi-seon Park
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Publication number: 20170317213Abstract: A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure directly on a sidewall of the gate structure, and a source/drain layer on a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a silicon oxycarbonitride (SiOCN) pattern and a silicon dioxide (SiO2) pattern sequentially stacked.Type: ApplicationFiled: January 19, 2017Publication date: November 2, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Mi-Seon PARK, Gi-Gwan PARK, Tae-Jong LEE, Yong-Suk TAK, Ki-Yeon PARK
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Publication number: 20170222014Abstract: A device includes: a gate line on an active region of a substrate, a pair of source/drain regions in the active region on both sides of the gate line, a contact plug on at least one source/drain region out of the pair of source/drain regions; and a multilayer-structured insulating spacer between the gate line and the contact plug. The multilayer-structured insulating spacer may include an oxide layer, a first carbon-containing insulating layer covering a first surface of the oxide layer adjacent to the gate line, and a second carbon-containing insulating layer covering a second surface of the oxide layer, opposite to the first surface of the oxide layer, adjacent to the contact plug.Type: ApplicationFiled: January 9, 2017Publication date: August 3, 2017Inventors: Yong-suk Tak, Tae-jong Lee, Hyun-seung Kim, Bon-young Koo, Ki-yeon Park, Gi-gwan Park, Mi-seon Park
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Publication number: 20170200718Abstract: A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgassing prevention pattern sequentially stacked.Type: ApplicationFiled: December 20, 2016Publication date: July 13, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-Hyun CHOI, Yong-Suk TAK, Gi-Gwan PARK, Bon-Young KOO, Ki-Yeon PARK, Won-Oh SEO