Abstract: Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers.

Abstract: A material layer, a semiconductor device including the material layer, and methods of forming the material layer and the semiconductor device are provided herein. A method of forming a SiOCN material layer may include supplying a silicon source onto a substrate, supplying a carbon source onto the substrate, supplying an oxygen source onto the substrate, supplying a nitrogen source onto the substrate, and supplying hydrogen onto the substrate. When a material layer is formed according to a method of the present inventive concepts, a material layer having a high tolerance to wet etching and/or good electric characteristics may be formed, and may even be formed when the method is performed at a low temperature.

Abstract: A method of forming a SiOCN material layer, a material layer stack, a semiconductor device, a method of fabricating a semiconductor device, and a deposition apparatus, the method of forming a SiOCN material layer including providing a substrate; providing a silicon precursor onto the substrate; providing an oxygen reactant onto the substrate; providing a first carbon precursor onto the substrate; providing a second carbon precursor onto the substrate; and providing a nitrogen reactant onto the substrate, wherein the first carbon precursor and the second carbon precursor are different materials.

Abstract: An integrated circuit device includes a fin type active area protruding from a substrate and having an upper surface at a first level; a nanosheet extending in parallel to the upper surface of the fin type active area and comprising a channel area, the nanosheet being located at a second level spaced apart from the upper surface of the fin type active area; a gate disposed on the fin type active area and surrounding at least a part of the nanosheet, the gate extending in a direction crossing the fin type active area; a gate dielectric layer disposed between the nanosheet and the gate; a source and drain region formed on the fin type active area and connected to one end of the nanosheet; a first insulating spacer on the nanosheet, the first insulating spacer covering sidewalls of the gate; and a second insulating spacer disposed between the gate and the source and drain region in a space between the upper surface of the fin type active area and the nanosheet, the second insulating spacer having a multilayer st

Abstract: A semiconductor device includes a substrate including an active fin structure, a plurality of gate structures, a first spacer on sidewalls of each of the gate structures, and a second spacer on sidewalls of the first spacer. The active fin structure may extend in a first direction and including a plurality of active fins with adjacent active fins divided by a recess. Each of the plurality of gate structures may extend in a second direction crossing the first direction, and may cover the active fins. The first spacer may include silicon oxycarbonitride (SiOCN), and may have a first carbon concentration. The second spacer may include SiOCN and may have a second carbon concentration which is different from the first carbon concentration. The semiconductor device may have a low parasitic capacitance and good electrical characteristics.

Abstract: A semiconductor device includes a substrate including an active fin structure, a plurality of gate structures, a first spacer on sidewalls of each of the gate structures, and a second spacer on sidewalls of the first spacer. The active fin structure may extend in a first direction and including a plurality of active fins with adjacent active fins divided by a recess. Each of the plurality of gate structures may extend in a second direction crossing the first direction, and may cover the active fins. The first spacer may include silicon oxycarbonitride (SiOCN), and may have a first carbon concentration. The second spacer may include SiOCN and may have a second carbon concentration which is different from the first carbon concentration. The semiconductor device may have a low parasitic capacitance and good electrical characteristics.

Abstract: A method for manufacturing a semiconductor device includes forming a trench defining a plurality of active fins in a substrate, forming a sacrificial layer on the plurality of active fins, forming a sacrificial oxide layer, and removing the sacrificial oxide layer. The forming the sacrificial oxide layer includes heat-treating the sacrificial layer and surfaces of the plurality of active fins.

Abstract: Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers.

Abstract: Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers.

Abstract: A method for manufacturing a semiconductor device includes forming a trench defining a plurality of active fins in a substrate, forming a sacrificial layer on the plurality of active fins, forming a sacrificial oxide layer, and removing the sacrificial oxide layer. The forming the sacrificial oxide layer includes heat-treating the sacrificial layer and surfaces of the plurality of active fins.

Abstract: A method and an apparatus perform Mobile High-definition Link (MHL) signal filtering. The method of performing the Mobile High-definition Link (MHL) signal filtering in a terminal includes determining whether a transmission device for MHL signal transmission is connected; determining whether a call continues when the transmission device is connected; and determining whether to perform the MHL signal filtering in the terminal based on whether the call continues. Accordingly, there is an advantage of improving picture quality of an image output from a multimedia device by effectively removing a common mode noise even when an RF weak electric field is formed due to call generation.

Abstract: Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers.

Abstract: A multi layer electromagnetic wave absorber is provided. The absorber includes a surface layer comprising at least one of a dielectric lossy mixture and a magnetic lossy mixture, an absorption layer, laminated on a rear side of the surface layer, comprising: a dielectric lossy mixture having a higher loss than the dielectric lossy mixture for the surface layer, and a magnetic lossy mixture having a higher loss than the magnetic lossy mixture for the surface layer, and a boundary layer, laminated on a rear side of the absorption layer, comprising a conductive material.

Abstract: Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers.

Abstract: An electronic device may include a substrate, an oxide dielectric layer on the substrate, an interface layer on the oxide dielectric layer, and an electrode on the interface layer. The oxide dielectric layer may include an aluminum oxide layer between first and second zirconium oxide layers. The interface layer may have a first formation enthalpy, and the oxide dielectric layer may be between the substrate and the interface layer. The electrode may have a second formation enthalpy higher than the first formation enthalpy, and the interface layer may be between the oxide dielectric layer and the electrode.

Abstract: A method for controlling a temperature of a terminal and a terminal supporting the same are provided. A terminal supporting temperature control includes a temperature sensor for detecting a temperature of the terminal, and a controller for performing at least one of a first throttle procedure including driving the controller with a first preset driving frequency when the temperature of the terminal detected by the temperature sensor is a first preset temperature, and driving the controller with a second driving frequency higher than the first driving frequency when the temperature of the terminal is reduced to a second preset temperature lower than the first preset temperature, and a second throttle procedure including driving the controller with the first preset driving frequency for a first time, and driving the controller with the second driving frequency higher than the first driving frequency for a second time after the first time elapses.

Abstract: Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers.

Abstract: A method of manufacturing a semiconductor device, the method including: preparing a semiconductor substrate including a mold layer and a support layer disposed on the mold layer; forming multiple holes that pass through the mold layer and the support layer; forming multiple bottom electrodes in the holes; exposing at least a portion of the bottom electrodes by removing at least a portion of the mold layer; removing a portion of the bottom electrodes from an exposed surface of the bottom electrodes; and sequentially forming a dielectric layer and a top electrode layer on the bottom electrodes.

Abstract: An electronic device includes a lower layer, a complex dielectric layer on the lower layer, and an upper layer on the complex dielectric layer. The complex dielectric layer includes an amorphous metal silicate layer and a crystalline metal-based insulating layer thereon. Related fabrication methods are also discussed.

Abstract: Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.