Abstract: A method and an apparatus perform Mobile High-definition Link (MHL) signal filtering. The method of performing the Mobile High-definition Link (MHL) signal filtering in a terminal includes determining whether a transmission device for MHL signal transmission is connected; determining whether a call continues when the transmission device is connected; and determining whether to perform the MHL signal filtering in the terminal based on whether the call continues. Accordingly, there is an advantage of improving picture quality of an image output from a multimedia device by effectively removing a common mode noise even when an RF weak electric field is formed due to call generation.

Abstract: A method for controlling a temperature of a terminal and a terminal supporting the same are provided. A terminal supporting temperature control includes a temperature sensor for detecting a temperature of the terminal, and a controller for performing at least one of a first throttle procedure including driving the controller with a first preset driving frequency when the temperature of the terminal detected by the temperature sensor is a first preset temperature, and driving the controller with a second driving frequency higher than the first driving frequency when the temperature of the terminal is reduced to a second preset temperature lower than the first preset temperature, and a second throttle procedure including driving the controller with the first preset driving frequency for a first time, and driving the controller with the second driving frequency higher than the first driving frequency for a second time after the first time elapses.

Abstract: In a method of forming a target layer having a uniform composition of constituent materials, a first precursor including a first central atom and a ligand is chemisorbed on a first reaction site of an object. The ligand or the first central atom is then removed to form a second reaction site. A second precursor including a second central atom is then chemisorbed on the second reaction site.

Abstract: Provided are methods of removing water adsorbed or bonded to a surface of a semiconductor substrate, and methods of depositing an atomic layer using the method of removing water described herein. The method of removing water includes applying a chemical solvent to the surface of a semiconductor substrate, and removing the chemical solvent from the surface of the semiconductor substrate.

Abstract: Methods of forming a metal silicate layer and methods of fabricating a semiconductor device including the metal silicate layer are provided, the methods of forming the metal silicate layer include forming the metal silicate using a plurality of silicon precursors. The silicon precursors are homoleptic silicon precursors in which ligands bound to silicon have the same molecular structure.

Abstract: A multi layer electromagnetic wave absorber is provided. The absorber includes a surface layer comprising at least one of a dielectric lossy mixture and a magnetic lossy mixture, an absorption layer, laminated on a rear side of the surface layer, comprising: a dielectric lossy mixture having a higher loss than the dielectric lossy mixture for the surface layer, and a magnetic lossy mixture having a higher loss than the magnetic lossy mixture for the surface layer, and a boundary layer, laminated on a rear side of the absorption layer, comprising a conductive material.

Abstract: Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.

Abstract: Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.

Abstract: A display panel and a method of manufacturing the same are provided. The display panel includes a plurality of chip panels, each chip panel having an upper surface, a lower surface disposed parallel to the upper surface, a side surface between the upper surface and the lower surface and a connection portion between the side surface and at least one of the upper surface and the lower surface, the connection portion having a rounded configuration, and an adhesive layer interposed between the chip panels in order to vertically stack the chip panels to connect the chip panels. Therefore, in the display panel, the strength of the edge portion can be improved. Also, by forming a connection portion, a stress can be suppressed from being concentrated at the edge portion by an external mechanical stress.

Abstract: An electronic device includes a lower layer, a complex dielectric layer on the lower layer, and an upper layer on the complex dielectric layer. The complex dielectric layer includes an amorphous metal silicate layer and a crystalline metal-based insulating layer thereon. Related fabrication methods are also discussed.

Abstract: Methods of forming a metal silicate layer and methods of fabricating a semiconductor device including the metal silicate layer are provided, the methods of forming the metal silicate layer include forming the metal silicate using a plurality of silicon precursors. The silicon precursors are homoleptic silicon precursors in which ligands bound to silicon have the same molecular structure.

Abstract: A semiconductor device and/or gate structure having a composite dielectric layer and methods of manufacturing the same is provided. In the semiconductor device, gate structure, and methods provided, a first conductive layer may be formed on a substrate. A native oxide layer formed on the first conductive layer may be removed. A surface of the first conductive layer may be nitrided so that the surface may be altered into a nitride layer. A composite dielectric layer including the first and/or second dielectric layers may be formed on the nitride layer. A second conductive layer may be formed on the composite dielectric layer. The first dielectric layer may include a material having a higher dielectric constant. The second dielectric layer may be capable of suppressing crystallization of the first dielectric layer.

Abstract: A method of forming a dielectric thin film of a semiconductor device, the method including supplying a first nuclear atom precursor source and a second nuclear atom precursor source having different thermal decomposition temperatures to a substrate and forming a chemical adsorption layer including first nuclear atoms and second nuclear atoms on the substrate. A reactant including oxygen atoms may be supplied to the substrate on which the chemical adsorption layer is formed. An atomic layer including an oxide of the first nuclear atoms and the second nuclear atoms may be formed on the chemical adsorption layer.

Abstract: A nonvolatile memory device includes a semiconductor substrate, a tunneling insulation layer on the semiconductor substrate, a charge storage layer on the tunneling insulation layer, an inter-electrode insulation layer on the charge storage layer, and a control gate electrode on the inter-electrode insulation layer. The inter-electrode insulation layer includes a high-k dielectric layer having a dielectric constant greater than that of a silicon nitride, and an interfacial layer between the charge storage layer and the high-k dielectric layer. The interfacial layer includes a silicon oxynitride layer.

Abstract: Provided are methods of removing water adsorbed or bonded to a surface of a semiconductor substrate, and methods of depositing an atomic layer using the method of removing water described herein. The method of removing water includes applying a chemical solvent to the surface of a semiconductor substrate, and removing the chemical solvent from the surface of the semiconductor substrate.

Abstract: In a method of forming a target layer having a uniform composition of constituent materials, a first precursor including a first central atom and a ligand is chemisorbed on a first reaction site of an object. The ligand or the first central atom is then removed to form a second reaction site. A second precursor including a second central atom is then chemisorbed on the second reaction site.

Abstract: In a non-volatile memory device and a method of manufacturing the non-volatile memory device, a tunnel insulating layer, a charge trapping layer, a dielectric layer and a conductive layer may be sequentially formed on a channel region of a substrate. The conductive layer may be patterned to form a gate electrode and spacers may be formed on sidewalls of the gate electrode. A dielectric layer pattern, a charge trapping layer pattern, and a tunnel insulating layer pattern may be formed on the channel region by an anisotropic etching process using the spacers as an etch mask. Sidewalls of the charge trapping layer pattern may be removed by an isotropic etching process to reduce the width thereof. Thus, the likelihood of lateral diffusion of electrons may be reduced or prevented in the charge trapping layer pattern and high temperature stress characteristics of the non-volatile memory device may be improved.

Abstract: In a gate structure of a non-volatile memory device is formed, a tunnel insulating layer and a charge trapping layer are formed on a substrate. A composite dielectric layer is formed on the charge trapping layer and has a laminate structure in which first material layers including aluminum oxide and second material layers including hafnium oxide or zirconium oxide are alternately stacked. A conductive layer is formed on the composite dielectric layer and then a gate structure is formed by patterning the conductive layer, the composite dielectric layer, the charge trapping layer, and the tunnel insulating layer.

Abstract: In a non-volatile memory device and a method of manufacturing the non-volatile memory device, a tunnel insulating layer, a charge trapping layer, a dielectric layer and a conductive layer may be sequentially formed on a channel region of a substrate. The conductive layer may be patterned to form a gate electrode and spacers may be formed on sidewalls of the gate electrode. A dielectric layer pattern, a charge trapping layer pattern, and a tunnel insulating layer pattern may be formed on the channel region by an anisotropic etching process using the spacers as an etch mask. Sidewalls of the charge trapping layer pattern may be removed by an isotropic etching process to reduce the width thereof. Thus, the likelihood of lateral diffusion of electrons may be reduced or prevented in the charge trapping layer pattern and high temperature stress characteristics of the non-volatile memory device may be improved.

Abstract: A method of manufacturing a non-volatile memory device includes forming a tunnel insulating layer on a substrate, forming a conductive pattern on the tunnel insulating layer, forming a lower dielectric layer on the conductive pattern, performing a first heat treatment process to density the lower dielectric layer, and forming a middle dielectric layer having an energy band gap smaller than that of the lower dielectric layer on the first heat-treated lower dielectric layer. The method further includes forming an upper dielectric layer including a material substantially identical to that of the lower dielectric layer on the middle dielectric layer, performing a second heat treatment process to densify the middle dielectric layer and the upper dielectric layer and forming a conductive layer on the second heat-treated upper dielectric layer.