Patents by Inventor Kiyoyuki Morita
Kiyoyuki Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040084727Abstract: A learning method of a semiconductor device of the present invention comprises a neuro device having a multiplier as a synapse in which a weight varies according to an input weight voltage, and functioning as a neural network system that processes analog data, comprising a step A of inputting predetermined input data to the neuro device and calculating an error between a target value of an output of the neuro device with respect to the input data and an actual output, a step B of calculating variation amount in the error by varying a weight of the multiplier thereafter, and a step C of varying the weight of the multiplier based on the variation amount in the error, wherein in the steps B and C, after inputting a reset voltage for setting the weight to a substantially constant value to the multiplier as the weight voltage, the weight is varied by inputting the weight voltage corresponding to the weight to be varied.Type: ApplicationFiled: May 9, 2003Publication date: May 6, 2004Inventors: Michihito Ueda, Kenji Toyoda, Takashi Ohtsuka, Kiyoyuki Morita
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Patent number: 6720596Abstract: A nonvolatile semiconductor storage element, which is provided with a floating gate electrode, and a dielectric capacitor and a ferroelectric capacitor both connected to the floating gate electrode. By applying voltage between a first polarization voltage supplying terminal and a second polarization voltage supplying terminal, polarization serving as information is generated in the ferroelectric film of the ferroelectric capacitor. Additionally, when a read-out voltage is applied between the ground terminal and the power source voltage terminal that are in connection with the source and drain regions, the MISFET is turned either on or off in correspondence to the state of the charge held in the floating gate electrode, and thus information within the floating gate electrode is read out.Type: GrantFiled: October 16, 2001Date of Patent: April 13, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takashi Ohtsuka, Kiyoyuki Morita, Michihito Ueda
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Patent number: 6720586Abstract: The method of fabricating a nitride semiconductor of this invention includes the steps of forming, on a substrate, a first nitride semiconductor layer of AluGavInwN, wherein 0≦u, v, w ≦1 and u+v+w=1; forming, in an upper portion of the first nitride semiconductor layer, plural convexes extending at intervals along a substrate surface direction; forming a mask film for covering bottoms of recesses formed between the convexes adjacent to each other; and growing, on the first nitride semiconductor layer, a second nitride semiconductor layer of AlxGayInzN, wherein 0≦x, y, z≦1 and x+y+z=1, by using, as a seed crystal, Cplanes corresponding to top faces of the convexes exposed from the mask film.Type: GrantFiled: November 15, 2000Date of Patent: April 13, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Isao Kidoguchi, Akihiko Ishibashi, Ryoko Miyanaga, Gaku Sugahara, Masakatsu Suzuki, Masahiro Kume, Yuzaburo Ban, Kiyoyuki Morita, Ayumu Tsujimura, Yoshiaki Hasegawa
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Patent number: 6716663Abstract: A semiconductor substrate is placed within a housing. By supplying organometallic complexes and carbon dioxide in a supercritical state into the housing, a BST thin film is formed on a platinum thin film, while at the same time, carbon compounds, which are produced when the BST thin film is formed, are removed. The solubility of carbon compounds in the supercritical carbon dioxide is very high, and yet the viscosity of the supercritical carbon dioxide is low. Accordingly, the carbon compounds are removable efficiently from the BST thin film. An oxide or nitride film may also be formed by performing oxidation or nitriding at a low temperature using water in a supercritical or subcritical state, for example.Type: GrantFiled: August 29, 2002Date of Patent: April 6, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoyuki Morita, Takashi Ohtsuka, Michihito Ueda
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Patent number: 6713316Abstract: A semiconductor substrate is placed within a housing. By supplying organometallic complexes and carbon dioxide in a supercritical state into the housing, a BST thin film is formed on a platinum thin film, while at the same time, carbon compounds, which are produced when the BST thin film is formed, are removed. The solubility of carbon compounds in the supercritical carbon dioxide is very high, and yet the viscosity of the supercritical carbon dioxide is low. Accordingly, the carbon compounds are removable efficiently from the BST thin film. An oxide or nitride film may also be formed by performing oxidation or nitriding at a low temperature using water in a supercritical or subcritical state, for example.Type: GrantFiled: August 29, 2002Date of Patent: March 30, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoyuki Morita, Takashi Ohtsuka, Michihito Ueda
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Patent number: 6689311Abstract: A method for selectively and rapidly extracting/removing a plasticizer from a compact such as a green laminate that is produced at a certain point in the process of manufacturing a multilayer ceramic capacitor. Carbon dioxide is introduced into a pressure chamber in which the green laminate has been placed, and the temperature and the pressure of the pressure chamber are set to 40° C. and 10 MPa, respectively, so that the pressure chamber is filled with a supercritical carbon dioxide. The plasticizer is extracted/removed from the green laminate by using the supercritical carbon dioxide. Then, a de-binder step and a baking step are performed in an ordinary manner. By performing the de-plasticizer process of selectively extracting/removing the plasticizer before the de-binder step, it is possible to suppress the formation of a graphite-like substance even if the temperature is increased rapidly in the subsequent de-binder step and the baking step.Type: GrantFiled: November 9, 2001Date of Patent: February 10, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoyuki Morita, Hideyuki Okinaka, Gen Itakura
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Publication number: 20040001374Abstract: A non-volatile memory (1) which comprises an insulating substrate (11) having a plurality of first electrodes (15) extending therethrough from a front surface of the substrate to a rear surface thereof, a second electrode (12) formed on one surface side of the substrate (11), and a recording layer (14) held between the first electrodes (15) and the second electrode (12) and variable in resistance value by electric pulses applied across the first electrodes (15) and the second electrode (12), the plurality of first electrodes (15) being electrically connected to the recording layer (14) in a region constituting a single memory cell (MC). The non-volatile memory (1) can be reduced in power consumption and has great freedom of design and high reliability.Type: ApplicationFiled: June 30, 2003Publication date: January 1, 2004Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Hideyuki Tanaka, Takashi Ohtsuka, Kiyoyuki Morita, Morimoto Kiyoshi
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Publication number: 20030198077Abstract: A semiconductor device includes: a control-voltage supply unit 110; an MOS transistor including a gate electrode 109 and drain and source regions 103a and 103b; a dielectric capacitor 104; and a resistor 106. The dielectric capacitor 104 and the resistor 106 are disposed in parallel and interposed between the gate electrode 109 and the control-voltage supply unit 110. With this structure, a charge is accumulated in each of an intermediate electrode of the dielectric capacitor 104 and the gate electrode 109 upon the application of a voltage, thereby varying a threshold value of the MOS transistor. In this manner, the history of input signals can be stored as a variation in a drain current in the MOS transistor, thus allowing multilevel information to be held.Type: ApplicationFiled: May 5, 2003Publication date: October 23, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTDInventors: Michihito Ueda, Takashi Ohtsuka, Kiyoyuki Morita
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Publication number: 20030197548Abstract: A potential generating circuit comprises a capacitor (4); a ferroelectric capacitor (6) connected in series to the capacitor (4); an output terminal (11); a capacitor (10) for grounding the output terminal (11); a switch (9) for connecting a connecting node (5) between the two capacitors (4, 6) to the output terminal (11); and a switch (1) for connecting the connecting node (5) to the ground; wherein during a first period, with the switches (1) and (9) placed in the OFF state, a terminal (3) is provided with a positive potential and a terminal (7) is grounded; wherein during a second period following the first period, the terminal (3) is grounded and the switch (9) is placed in the ON state; wherein during a third period following the second period, the switch (9) is placed in the OFF state, the switch (1) is placed in the ON state, and the terminal (7) is provided with a positive potential; wherein during a fourth period following the third period, the terminal (7) is grounded; and wherein the first throughType: ApplicationFiled: May 16, 2003Publication date: October 23, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kenji Toyoda, Michihito Ueda, Kiyoshi Morimoto, Kiyoyuki Morita, Toru Iwata, Jun Kajiwara
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Publication number: 20030143771Abstract: The method of fabricating a nitride semiconductor of this invention includes the steps of forming, on a substrate, a first nitride semiconductor layer of AluGavInwN, wherein 0≦u, v, w≦1 and u+v+w=1; forming, in an upper portion of the first nitride semiconductor layer, plural convexes extending at intervals along a substrate surface direction; forming a mask film for covering bottoms of recesses formed between the convexes adjacent to each other; and growing, on the first nitride semiconductor layer, a second nitride semiconductor layer of AlxGayInzN, wherein 0≦x, y, z≦1 and x+y+z=1, by using, as a seed crystal, C planes corresponding to top faces of the convexes exposed from the mask film.Type: ApplicationFiled: January 16, 2003Publication date: July 31, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Isao Kidoguchi, Akihiko Ishibashi, Ryoko Miyanaga, Gaku Sugahara, Masakatsu Suzuki, Masahiro Kume, Yuzaburo Ban, Kiyoyuki Morita, Ayumu Tsujimura, Yoshiaki Hasegawa
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Publication number: 20030142533Abstract: A semiconductor device includes: a control-voltage supply unit 110; an MOS transistor including a gate electrode 109 and drain and source regions 103a and 103b; a dielectric capacitor 104; and a resistor 106. The dielectric capacitor 104 and the resistor 106 are disposed in parallel and interposed between the gate electrode 109 and the control-voltage supply unit 110. With this structure, a charge is accumulated in each of an intermediate electrode of the dielectric capacitor 104 and the gate electrode 109 upon the application of a voltage, thereby varying a threshold value of the MOS transistor. In this manner, the history of input signals can be stored as a variation in a drain current in the MOS transistor, thus allowing multilevel information to be held.Type: ApplicationFiled: March 6, 2003Publication date: July 31, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Michihito Ueda, Takashi Ohtsuka, Kiyoyuki Morita
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Publication number: 20030132432Abstract: The semiconductor device of the present invention includes: particles or interface states for passing charge formed on a p-type silicon substrate via a barrier layer; and particles for holding charge formed above the charge-passing particles via another barrier layer. The charge-holding particles are different from the charge-passing particles in parameters such as the particle diameter, the capacitance, the electron affinity, and the sum of electron affinity and forbidden bandwidth, to attain swift charge injection and release as well as stable charge holding in the charge-holding particles.Type: ApplicationFiled: January 24, 2003Publication date: July 17, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Shigeo Yoshii, Kiyoshi Morimoto, Kiyoyuki Morita, Haruyuki Sorada
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Publication number: 20030094640Abstract: A nonvolatile semiconductor storage element, which is provided with a floating gate electrode, and a dielectric capacitor and a ferroelectric capacitor both connected to the floating gate electrode. By applying voltage between a first polarization voltage supplying terminal and a second polarization voltage supplying terminal, polarization serving as information is generated in the ferroelectric film of the ferroelectric capacitor. Additionally, when a read-out voltage is applied between the ground terminal and the power source voltage terminal that are in connection with the source and drain regions, the MISFET is turned either on or off in correspondence to the state of the charge held in the floating gate electrode, and thus information within the floating gate electrode is read out.Type: ApplicationFiled: December 31, 2002Publication date: May 22, 2003Applicant: Matsushit Electric Industrial Co., Ltd.Inventors: Takashi Ohtsuka, Kiyoyuki Morita, Michihito Ueda
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Patent number: 6548825Abstract: The semiconductor device of the present invention includes: particles or interface states for passing charge formed on a p-type silicon substrate via a barrier layer; and particles for holding charge formed above the charge-passing particles via another barrier layer. The charge-holding particles are different from the charge-passing particles in parameters such as the particle diameter, the capacitance, the electron affinity, and the sum of electron affinity and forbidden bandwidth, to attain swift charge injection and release as well as stable charge holding in the charge-holding particles.Type: GrantFiled: June 5, 2000Date of Patent: April 15, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shigeo Yoshii, Kiyoshi Morimoto, Kiyoyuki Morita, Haruyuki Sorada
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Patent number: 6541278Abstract: A semiconductor substrate is placed within a housing. By supplying organometallic complexes and carbon dioxide in a supercritical state into the housing, a BST thin film is formed on a platinum thin film, while at the same time, carbon compounds, which are produced when the BST thin film is formed are removed. The solubility of carbon compounds in the supercritical carbon dioxide is very high, and yet the viscosity of the supercritical carbon dioxide is low. Accordingly, the carbon compounds are removable efficiently from the BST thin film. An oxide or nitride film may also be formed by performing oxidation or nitriding at a low temperature using water in a supercritical or subcritical state, for example.Type: GrantFiled: January 27, 2000Date of Patent: April 1, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoyuki Morita, Takashi Ohtsuka, Michihito Ueda
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Patent number: 6538297Abstract: A magneto-resistive device and a magneto-resistive effect type storage device are provided, which have improved selectivity and output signals by controlling bias to be applied. Two resistive devices are connected in series, and a magneto-resistive device is used for at least one of the resistive devices. When both of the resistive devices are magneto-resistive devices, their magnetic resistance should be controlled independently from each other, and by allowing the first magneto-resistive device to include a nonmagnetic substance of an electrical insulator and the second magneto-resistive device to include a nonmagnetic substance of a conductive substance, the second magneto-resistive device is operated as a bias control device for controlling the characteristics of the first magneto-resistive device so as to control the voltage to be applied to the storage device.Type: GrantFiled: March 13, 2001Date of Patent: March 25, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akihiro Odagawa, Hiroshi Sakakima, Kiyoyuki Morita
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Patent number: 6503360Abstract: A subcritical or supercritical water is used to selectively etch a silicon nitride film against a silicon dioxide film or to selectively etch a silicon dioxide film against a crystalline silicon region. This method is applicable to a process of forming a MISFET or a charge emitting device.Type: GrantFiled: July 17, 2001Date of Patent: January 7, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Kiyoyuki Morita
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Publication number: 20030003770Abstract: A semiconductor substrate is placed within a housing. By supplying organometallic complexes and carbon dioxide in a supercritical state into the housing, a BST thin film is formed on a platinum thin film, while at the same time, carbon compounds, which are produced when the BST thin film is formed, are removed. The solubility of carbon compounds in the supercritical carbon dioxide is very high, and yet the viscosity of the supercritical carbon dioxide is low. Accordingly, the carbon compounds are removable efficiently from the BST thin film. An oxide or nitride film may also be formed by performing oxidation or nitriding at a low temperature using water in a supercritical or subcritical state, for example.Type: ApplicationFiled: August 29, 2002Publication date: January 2, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kiyoyuki Morita, Takashi Ohtsuka, Michihito Ueda
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Publication number: 20030003604Abstract: A semiconductor substrate is placed within a housing. By supplying organometallic complexes and carbon dioxide in a supercritical state into the housing, a BST thin film is formed on a platinum thin film, while at the same time, carbon compounds, which are produced when the BST thin film is formed, are removed. The solubility of carbon compounds in the supercritical carbon dioxide is very high, and yet the viscosity of the supercritical carbon dioxide is low. Accordingly, the carbon compounds are removable efficiently from the BST thin film. An oxide or nitride film may also be formed by performing oxidation or nitriding at a low temperature using water in a supercritical or subcritical state, for example.Type: ApplicationFiled: August 29, 2002Publication date: January 2, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kiyoyuki Morita, Takashi Ohtsuka, Michihito Ueda
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Publication number: 20020185690Abstract: In an electric potential generating device, a source of an N type MIS transistor is mutually connected to that of a P type MIS transistor and also connected to an output terminal. A drain of an N type MIS transistor 54 is connected to a power supply voltage supply portion for supplying power supply voltage VDD, and a drain of the P type MIS transistor is connected to a ground. In addition, a substrate potential of the N type MIS transistor is a ground voltage VSS, and that of a P type MIS transistor 56 is the power supply voltage VDD. Thus, it is constituted as a source follower circuit for taking output out of the source. It is possible, by utilizing this electric potential generating device, to obtain a logic transformation circuit for stably switching between NOR operation and NAND operation.Type: ApplicationFiled: June 5, 2002Publication date: December 12, 2002Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Michihito Ueda, Kenji Toyoda, Kiyoyuki Morita, Takashi Ohtsuka