Patents by Inventor Kiyoyuki Morita

Kiyoyuki Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5304515
    Abstract: A method and apparatus for forming a dielectric thin film or pattern thereof is provided in which a positive or negative resist of a desired pattern is formed on various substrates including a semiconductor substrate by contact of the resist with a liquefied gas or super critical fluid of CO.sub.2, NH.sub.3 or the like. Alternatively, a thin film of an organic or inorganic compound dissolved or dispersed in an organic solvent which has been formed on substrate becomes substantially free of any organic matter or functional groups by contact with the liquefied gas or super critical fluid. Semiconductor devices of high performance and high reliability are ensured.
    Type: Grant
    Filed: August 7, 1992
    Date of Patent: April 19, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoyuki Morita, Takeshi Ishihara
  • Patent number: 5273914
    Abstract: An ion implantation stopper is formed on a gate electrode extending on a substrate. When ions are implanted into the substrate to form an LDD layer or source and drain regions in the substrate, the stopper functions to prevent the gate electrode from being exposed to ion implantation. The prevention of the exposure of the gate electrode to the ion implantation ensures the prevention of channeling in the gate electrode. The invention includes forming a first protective film on the gate of an NMOS, implanting to form LDD region for the NMOS, implanting to form source and drain regions of a PMOS, forming a second protective film on the gate of the NMOS, implanting to form source and drain regions of the NMOS, the first and second protective films prevent the gate electrode of the NMOS from being exposed to ion implantation during the respective implanting steps so that channeling is prevented from occurring in the gate electrode of the NMOS.
    Type: Grant
    Filed: June 19, 1992
    Date of Patent: December 28, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akio Miyajima, Keiichi Kagawa, Akihira Shinohara, Kiyoyuki Morita, Takashi Uehara
  • Patent number: 5185296
    Abstract: A method and apparatus for forming a dielectric thin film or pattern thereof is provided in which a positive or negative resist of a desired pattern if formed on various substrates including a semiconductor substrate by contact of the resist with a liquefied gas or super critical fluid of CO.sub.2, NH.sub.3 or the like. Alternatively, a thin film of an organic or inorganic compound dissolved or dispersed in an organic solvent which has been formed on substrate becomes substantially free of any organic matter or functional groups by contact with the liquefied gas or super critical fluid. Semiconductor devices of high performance and high reliability are ensured.
    Type: Grant
    Filed: April 24, 1991
    Date of Patent: February 9, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoyuki Morita, Takeshi Ishihara
  • Patent number: 5030582
    Abstract: An ion implantation stopper is formed on a gate electrode extending on a substrate. When ions are implanted into the substrate to form an LDD layer or source and drain regions in the substrate, the stopper functions to prevent the gate electrode from being exposed to ion implantation. The prevention of the exposure of the gate electrode to the ion implantation ensures the prevention of channeling in the gate electrode.
    Type: Grant
    Filed: October 6, 1989
    Date of Patent: July 9, 1991
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akio Miyajima, Keiichi Kagawa, Akihira Shinohara, Kiyoyuki Morita, Takashi Uehara