Patents by Inventor Kiyoyuki Morita

Kiyoyuki Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6475403
    Abstract: A subcritical or supercritical water is used to selectively etch a silicon nitride film against a silicon dioxide film or to selectively etch a silicon dioxide film against a crystalline silicon region. This method is applicable to a process of forming a MISFET or a charge emitting device.
    Type: Grant
    Filed: January 30, 2001
    Date of Patent: November 5, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kiyoyuki Morita
  • Publication number: 20020142163
    Abstract: The present invention provides aligned fine particles that are aligned on a substrate. An organic coating film is bonded to surfaces of the fine particles is formed on the surfaces of the fine particles. An organic coating film bonded to a surface of the substrate is formed on the surface of the substrate. The organic coating film on the surfaces of the fine particles is bonded to the organic coating film on the surface of the substrate, whereby the fine particles are immobilized and aligned on the substrate. Thus, it is possible to align the fine particles of a nanometer scale in a specific direction. When fine magnetic particles are used, a magnetic recording medium for high recording density can be obtained, and a high-density magnetic recording/reproducing apparatus can be provided.
    Type: Application
    Filed: January 22, 2002
    Publication date: October 3, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Norihisa Mino, Yasuhiro Kawawake, Kiyoyuki Morita, Shigeo Yoshii, Mutuaki Murakami, Osamu Kusumoto
  • Publication number: 20020083959
    Abstract: A semiconductor substrate is placed within a housing. By supplying organometallic complexes and carbon dioxide in a supercritical state into the housing, a BST thin film is formed on a platinum thin film, while at the same time, carbon compounds, which are produced when the BST thin film is formed, are removed. The solubility of carbon compounds in the supercritical carbon dioxide is very high, and yet the viscosity of the supercritical carbon dioxide is low. Accordingly, the carbon compounds are removable efficiently from the BST thin film. An oxide or nitride film may also be formed by performing oxidation or nitriding at a low temperature using water in a supercritical or subcritical state, for example.
    Type: Application
    Filed: January 27, 2000
    Publication date: July 4, 2002
    Inventors: Kiyoyuki Morita, Takashi Ohtsuka, Michihito Ueda
  • Publication number: 20020057980
    Abstract: A method for selectively and rapidly extracting/removing a plasticizer from a compact such as a green laminate that is produced at a certain point in the process of manufacturing a multilayer ceramic capacitor. Carbon dioxide is introduced into a pressure chamber in which the green laminate has been placed, and the temperature and the pressure of the pressure chamber are set to 40° C. and 10 MPa, respectively, so that the pressure chamber is filled with a supercritical carbon dioxide. The plasticizer is extracted/removed from the green laminate by using the supercritical carbon dioxide. Then, a de-binder step and a baking step are performed in an ordinary manner. By performing the de-plasticizer process of selectively extracting/removing the plasticizer before the de-binder step, it is possible to suppress the formation of a graphite-like substance even if the temperature is increased rapidly in the subsequent de-binder step and the baking step.
    Type: Application
    Filed: November 9, 2001
    Publication date: May 16, 2002
    Inventors: Kiyoyuki Morita, Hideyuki Okinaka, Gen Itakura
  • Publication number: 20020043676
    Abstract: A nonvolatile semiconductor storage element, which is provided with a floating gate electrode, and a dielectric capacitor and a ferroelectric capacitor both connected to the floating gate electrode. By applying voltage between a first polarization voltage supplying terminal and a second polarization voltage supplying terminal, polarization serving as information is generated in the ferroelectric film of the ferroelectric capacitor. Additionally, when a read-out voltage is applied between the ground terminal and the power source voltage terminal that are in connection with the source and drain regions, the MISFET is turned either on or off in correspondence to the state of the charge held in the floating gate electrode, and thus information within the floating gate electrode is read out.
    Type: Application
    Filed: October 16, 2001
    Publication date: April 18, 2002
    Inventors: Takashi Ohtsuka, Kiyoyuki Morita, Michihito Ueda
  • Patent number: 6342716
    Abstract: A semiconductor device as a nonvolatile memory comprises dot elements which are formed out of the semiconductor or conductor fine particles and function as a floating gate. The dot elements are asymmetrically formed to a control gate and may be formed in a sidewall insulating film formed over the side face of the control gate or a select gate. When inclined or stepped portions having level differences are formed in a semiconductor substrate, the dot elements are formed on a specified portion of the inclined or stepped portions.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: January 29, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoyuki Morita, Kiyoshi Morimoto, Kiyoshi Araki, Koichiro Yuki, Kazuyasu Adachi, Masayuki Endo, Ichiro Yamashita
  • Publication number: 20010037860
    Abstract: A subcritical or supercritical water is used to selectively etch a silicon nitride film against a silicon dioxide film or to selectively etch a silicon dioxide film against a crystalline silicon region. This method is applicable to a process of forming a MISFET or a charge emitting device.
    Type: Application
    Filed: July 17, 2001
    Publication date: November 8, 2001
    Inventor: Kiyoyuki Morita
  • Patent number: 6303516
    Abstract: A Rat IgG antibody film, formed on a p-type Si substrate, is selectively irradiated with ultraviolet rays, thereby leaving part of the Rat IgG antibody film, except for a region deactivated with the ultraviolet rays. Next, when the p-type Si substrate is immersed in a solution containing Au fine particles that have been combined with a Rat IgG antigen, the Rat IgG antigen is selectively combined with the Rat IgG antibody film. As a result, Au fine particles, combined with the Rat IgG antigen, are fixed on the Rat IgG antibody film. Thereafter, the p-type Si substrate is placed within oxygen plasma for 20 minutes, thereby removing the Rat IgG antibody film, the deactivated Rat IgG antibody film and the Rat IgG antigen. Consequently, dot elements can be formed at desired positions on the p-type Si substrate. If these dot elements are used for the floating gate of a semiconductor memory device, then the device has a structure suitable for miniaturization.
    Type: Grant
    Filed: December 10, 1998
    Date of Patent: October 16, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoyuki Morita, Kiyoshi Morimoto, Kiyoshi Araki, Koichiro Yuki, Kazuyasu Adachi, Masayuki Endo, Ichiro Yamashita
  • Publication number: 20010021124
    Abstract: A magneto-resistive device and a magneto-resistive effect type storage device are provided, which have improved selectivity and output signals by controlling bias to be applied. Two resistive devices are connected in series, and a magneto-resistive device is used for at least one of the resistive devices. When both of the resistive devices are magneto-resistive devices, their magnetic resistance should be controlled independently from each other, and by allowing the first magneto-resistive device to include a nonmagnetic substance of an electrical insulator and the second magneto-resistive device to include a nonmagnetic substance of a conductive substance, the second magneto-resistive device is operated as a bias control device for controlling the characteristics of the first magneto-resistive device so as to control the voltage to be applied to the storage device.
    Type: Application
    Filed: March 13, 2001
    Publication date: September 13, 2001
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiro Odagawa, Hiroshi Sakakima, Kiyoyuki Morita
  • Publication number: 20010010306
    Abstract: A subcritical or supercritical water is used to selectively etch a silicon nitride film against a silicon dioxide film or to selectively etch a silicon dioxide film against a crystalline silicon region. This method is applicable to a process of forming a MISFET or a charge emitting device.
    Type: Application
    Filed: January 30, 2001
    Publication date: August 2, 2001
    Inventor: Kiyoyuki Morita
  • Patent number: 6171905
    Abstract: The invention provides a semiconductor device, having a variety of functions such as a bistable memory and a logic circuit, in which a MOS semiconductor element, a resonance tunnel diode, a hot electron transistor and the like are formed on a common substrate. An n-type Si layer and a p-type Si layer surrounded with an isolation oxide film are formed on an SOI substrate. A mask oxide film and a gate oxide film are formed, and the n-type Si layer is subjected to crystal anisotropic etching by using the mask oxide film as a mask, so as to change the n-type Si layer into the shape of a thin Si plate. After first and second tunnel oxide films are formed on side faces of this n-type Si layer, first and second polysilicon electrodes of a resonance tunnel diode and a polysilicon electrode working as a gate electrode of a MOS semiconductor element are formed out of a common polysilicon film. Thus, a Si/SiO2 type quantum device can be manufactured with ease at a low cost.
    Type: Grant
    Filed: November 17, 1998
    Date of Patent: January 9, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoyuki Morita, Kiyoshi Morimoto, Koichiro Yuki, Kiyoshi Araki
  • Patent number: 6103583
    Abstract: A quantization functional device includes: a silicon thin layer having a first surface and a second surface each made of a predetermined crystal surface, and the silicon thin layer being formed of single crystalline silicon having a thickness sufficiently thin to function as a quantum well; a pair of tunnel barriers respectively provided on the first and second surfaces of the silicon thin layer; and a first electrode and a second electrode operatively coupled to each other and formed so as to interpose the silicon thin layer and the pair of the tunnel barriers therebetween.
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: August 15, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Morimoto, Koichiro Yuki, Yoshihiko Hirai, Kiyoyuki Morita
  • Patent number: 6091077
    Abstract: The invention provides a semiconductor device, having a variety of functions such as a bistable memory and a logic circuit, in which a MOS semiconductor element, a resonance tunnel diode, a hot electron transistor and the like are formed on a common substrate. An n-type Si layer and a p-type Si layer surrounded with an isolation oxide film are formed on an SOI substrate. A mask oxide film and a gate oxide film are formed, and the n-type Si layer is subjected to crystal anisotropic etching by using the mask oxide film as a mask, so as to change the n-type Si layer into the shape of a thin Si plate. After first and second tunnel oxide films are formed on side faces of this n-type Si layer, first and second polysilicon electrodes of a resonance tunnel diode and a polysilicon electrode working as a gate electrode of a MOS semiconductor element are formed out of a common polysilicon film. Thus, a Si/SiO.sub.2 type quantum device can be manufactured with ease at a low cost.
    Type: Grant
    Filed: October 21, 1997
    Date of Patent: July 18, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoyuki Morita, Kiyoshi Morimoto, Koichiro Yuki, Kiyoshi Araki
  • Patent number: 6015978
    Abstract: The method for forming a semiconductor microstructure of this invention includes the steps of: forming a mask pattern having a first opening and a second opening on a substrate having a semiconductor layer as an upper portion thereof; and selectively etching the semiconductor layer using the mask pattern to form a semiconductor microstructure extending in a first direction parallel to a surface of the substrate, wherein, in the step of selectively etching the semiconductor layer, an etching rate in a second direction vertical to the first direction and parallel to the surface of the substrate is substantially zero with respect to an etching rate in the first direction, and a width of the semiconductor microstructure is substantially equal to a shortest distance between the first opening and the second opening in the second direction.
    Type: Grant
    Filed: October 20, 1998
    Date of Patent: January 18, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichiro Yuki, Kiyoyuki Morita, Kiyoshi Morimoto, Yoshihiko Hirai
  • Patent number: 5972744
    Abstract: A silicon island portion is formed in a quantum wire so as to be sandwiched between a pair of tunnel barrier portions of a silicon oxide film. On one side of the silicon island portion, a gate electrode for potential control is disposed with a gate insulating film of a silicon oxide film interposed therebetween. On the other side of the silicon island portion, a control electrode for potential control is disposed with an insulating film of a silicon oxide film interposed therebetween. Each of the tunnel barrier portions has a quantum wire constriction structure, which is formed by oxidizing a quantum wire, i.e., a silicon oxide film formed as a field enhanced oxide film with an atomic force microscope or the like, from its surface to a substantially center portion in its section.
    Type: Grant
    Filed: March 9, 1998
    Date of Patent: October 26, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Morimoto, Kiyoyuki Morita, Kiyoshi Araki, Yoshihiko Hirai, Koichiro Yuki
  • Patent number: 5945687
    Abstract: A quantization functional device includes: a silicon thin layer having a first surface and a second surface each made of a predetermined crystal surface, and the silicon thin layer being formed of single crystalline silicon having a thickness sufficiently thin to function as a quantum well; a pair of tunnel barriers respectively provided on the first and second surfaces of the silicon thin layer; and a first electrode and a second electrode operatively coupled to each other and formed so as to interpose the silicon thin layer and the pair of the tunnel barriers therebetween.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: August 31, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Morimoto, Koichiro Yuki, Yoshihiko Hirai, Kiyoyuki Morita
  • Patent number: 5909033
    Abstract: A recess portion in a bowl-like shape is formed at the center of a silicon substrate, and plural cathodes are formed in a matrix with a predetermined distance therebetween on the bottom of the recess portion. Around each cathode on the silicon substrate, a withdrawn electrode is formed with an insulating film disposed therebelow. A first wire layer connected with the withdrawn electrode at one end extends along a slant side face of the recess portion and on the top face of a protrusion portion. A sealing cover in the shape of a flat plate of a transparent glass plate or the like is integrated with the silicon substrate with a circular sealing material disposed therebetween. A space formed among the silicon substrate, the circular sealing material and the sealing cover is retained to be vacuated.
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: June 1, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keisuke Koga, Kiyoyuki Morita
  • Patent number: 5888852
    Abstract: The method for forming a semiconductor microstructure of this invention includes the steps of: forming a mask pattern having a first opening and a second opening on a substrate having a semiconductor layer as an upper portion thereof; and selectively etching the semiconductor layer using the mask pattern to form a semiconductor microstructure extending in a first direction parallel to a surface of the substrate, wherein, in the step of selectively etching the semiconductor layer, an etching rate in a second direction vertical to the first direction and parallel to the surface of the substrate is substantially zero with respect to an etching rate in the first direction, and a width of the semiconductor microstructure is substantially equal to a shortest distance between the first opening and the second opening in the second direction.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: March 30, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichiro Yuki, Kiyoyuki Morita, Kiyoshi Morimoto, Yoshihiko Hirai
  • Patent number: 5739544
    Abstract: By etching, a first groove and a second groove are formed in a silicon substrate. Surfaces of the side walls of these grooves have a surface orientation of (111). The first and second grooves sandwich a silicon thin plate therebetween, which is formed as a part of the silicon substrate. The silicon thin plate is sufficiently thin so as to act as a quantum well. Further, a pair of silicon oxide films acting as tunneling barriers are formed on the surfaces of the side walls of the silicon thin plate, thus forming a double barrier structure. In addition, a pair of polysilicon electrodes are formed and sandwich the double barrier structure. As a result, the structure of a resonance tunneling diode, which utilizes the resonance tunneling effect, is provided. Adding a third electrode to the above structure provides a resonance tunneling transistor.
    Type: Grant
    Filed: December 12, 1995
    Date of Patent: April 14, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichiro Yuki, Yoshihiko Hirai, Kiyoshi Morimoto, Masaaki Niwa, Juro Yasui, Kenji Okada, Masaharu Udagawa, Kiyoyuki Morita
  • Patent number: 5736421
    Abstract: Mounted on a single semiconductor substrate are a DRAM, MOS transistor, resistor, and capacitor. The gate electrode of the DRAM and the gate electrode of the MOS transistor are formed by a common layer (i.e., a first-level poly-Si layer). The storage electrode of the DRAM. the resistor, and the lower electrode of the capacitor are formed by a common layer (i.e., a third-level poly-Si layer). The plate electrode of the DRAM and the upper electrode of the capacitor are formed by a common layer (i.e., a fourth-level poly-Si layer).
    Type: Grant
    Filed: January 23, 1996
    Date of Patent: April 7, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroshi Shimomura, Kiyoyuki Morita, Takashi Nakabayashi, Takashi Uehara, Mitsuo Yasuhira, Mizuki Segawa, Takehiro Hirai