Abstract: A method for manufacturing a semiconductor device includes forming an interconnect in a first dielectric layer, and forming a second dielectric layer on the first dielectric layer. In the method, an etch stop layer is formed on the second dielectric layer, and a third dielectric layer is formed on the etch stop layer. A trench and an opening are formed in the third and second dielectric layers, respectively. A barrier layer is deposited in the trench and in the opening, and on a top surface of the interconnect. The method also includes removing the barrier layer from the top surface of the interconnect and from a bottom surface of the trench, and depositing a conductive fill layer in the trench and in the opening, and on the interconnect. A bottom surface of the trench includes the etch stop layer.

Abstract: A semiconductor structure including a first metal line, a top via above and directly contacting the first metal line, a second metal line adjacent to the first metal line, a first dielectric contacting sidewalls of the top via, a second dielectric directly between the first dielectric and the second metal line, and an air gap located between the first metal line and the second metal line, and below both the first dielectric and the second dielectric.

Abstract: A structure and a method for fabricating interconnections for an integrated circuit device are described. The method forms a metal interconnection pattern having a first barrier layer and a copper layer in a set of trenches in a first dielectric layer over a substrate. In a selected area, the first dielectric layer is removed to so that the first barrier layer can be removed at the exposed vertical surfaces. A thin second barrier layer is deposited over the exposed vertical surfaces of the first copper layer. A structure includes a first feature formed in a first dielectric layer which has a first barrier layer disposed on vertical surfaces of the first dielectric layer and surrounds opposing vertical surfaces and a bottom surface of a copper layer.

Abstract: Conductive lines, integrated chips, and methods of forming the same include forming a first metal liner in a trench in a substrate. The trench is filled with a second metal. The second metal is overpolished with a chemical mechanical planarization (CMP) process that stops on the first metal liner, such that the second metal is reduced to a level that is below a height of a top surface of the substrate. The trench is filled with a third metal.

Abstract: Method and a magnetoresistive random access memory (MRAM) structure is provided. The structure includes an interconnect and a multilayered magnetic tunnel junction (MTJ) pillar located on the interconnect and having an outermost sidewall. The MTJ pillar includes an electrode layer electrically connecting the MTJ pillar to the interconnect. The electrode layer includes an insulative material at an outermost portion of the electrode layer and a conductive material at a first inner portion of the electrode layer disposed radially inward from the outermost portion of the electrode layer.

Abstract: A first metal interconnection pattern is formed over a substrate. A spacer layer is selectively deposited on the exposed surfaces of the first metal interconnection pattern. Subsequently, a metal overburden layer is deposited on the spacer layer. The excess portion of the metal overburden layer is removed, i.e., that portion deposited over a top surface of the metal interconnection pattern and the spacer layer. This forms a second metal interconnection pattern. The elements of the second metal interconnection pattern are located between respective elements of the first metal interconnection pattern.

Abstract: Provided are embodiments for method of fabricating a dual damascene crossbar array. The method includes forming a bottom electrode layer on a substrate and forming a first memory device on the bottom electrode layer. The method also includes forming a dual damascene structure on the first memory device, wherein the dual damascene structure includes a top electrode layer and a first via, wherein the first via is formed between the first memory device and the top electrode layer. Also provided are embodiments for the dual damascene crossbar and embodiments for disabling memory devices of the dual damascene crossbar array.

Abstract: An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes a metal line layer and a top via layer that each include a plurality of alternating first layers composed of a first metal and second layers composed of a second metal, whereby the second layers are thinner than the first layers.

Abstract: An interconnect structure that in one embodiment can include a first metal line level having a first metal line, a second metal line level having a second metal line, and a via line level present between the first and second metal line levels. The via line level includes a via interlevel dielectric surrounding a via stack. The via stack may include an interface metal portion that is in contact with the first metal line, a via intralevel dielectric on the interface metal portion, and a cap metal portion in contact with the second metal line and extending through the via intralevel dielectric into contact with the interface metal portion. In some embodiments, the length of the interface metal portion of the via is greater than a width of the interface metal portion of the via stack.

Abstract: An electrical communication structure that includes a plurality of metal line levels, a first metal line in a first metal line level of the plurality of line levels, and a second metal line in an upper metal line level of the plurality of line levels. A base of the second metal line is atop a metal etch stop layer that is aligned with edges of the second metal line. The electrical communication structure further includes a via that extends from the first metal line to the second metal line through the plurality of line levels. the via is not in electrical communication with at least one an intermediate metal line within the plurality of line levels between the first metal line level and the upper metal line level. The via has a metal fill that is in direct contact with a metal fill of the first metal line.

Abstract: A computer-implemented method of assessing roughness in metallic lines of an integrated circuit (IC) is provided. The computer-implemented method includes developing a library of roughness characterizations for metal lines of varying characteristics and dimensions. The computer-implemented method further includes fabricating a testable IC and identifying, in the testable IC, a location of interest (LoI) at which roughness of a metal line within the LoI could impact IC performance. Also, the computer-implemented method includes developing, from the library, a roughness model using the roughness characterizations for those metal lines having characteristics and dimensions corresponding to those of the metal line within the LoI and refining the library and the roughness model based on a comparison of the roughness model and an actual roughness of the metal line within the LoI to obtain a final roughness model.

Abstract: Embodiments of the invention are directed to a structure comprising a magnetic tunnel junction (MTJ) element and an etched bottom electrode (BE) communicatively coupled to the MTJ element. The etched BE includes a substantially non-planar BE sidewall.

Abstract: Embodiments disclosed herein describe semiconductor devices that include semiconductor structures and methods of forming the semiconductor structures. The methods may include forming a subtractive line from a bottom metal layer and a sacrificial hard mask above the bottom metal layer, depositing a scaffolding material around the subtractive line, forming a via mask over a via portion of the sacrificial hard mask and the scaffolding material, etching the sacrificial hard mask that is not covered by the via mask, to form a sacrificial via, removing the via mask and the scaffolding material, depositing a low-? layer around the subtractive line and the sacrificial via, removing the sacrificial via to form a via hole within the low-? layer, and forming a top via by metallizing the via hole.

Abstract: A MIM capacitor and related methods of fabricating the MIM capacitor. The MIM capacitor includes a bottom capacitor plate including a plurality of trenches defined therein, and a top capacitor plate. The MIM capacitor also includes a capacitor insulating layer disposed between the top capacitor plate and the bottom capacitor plate and within the plurality of trenches. Further, the MIM capacitor includes a first electrode electrically connected to the bottom capacitor plate, and a second electrode electrically connected to the top capacitor plate.

Abstract: The structure comprises a first low-k dielectric layer on top of a substrate. The structure comprises one or more trenches within the first low-k dielectric layer. The structure comprises a first barrier layer on the first low-k dielectric layer, a first liner layer on top of the first barrier layer and a first metal layer on top of the first liner layer, wherein a top of the first barrier layer, the first liner layer, and the first metal layer are at least 5 nm below a top of the first low-k dielectric layer. The structure comprises a dielectric cap between portions the first low-k dielectric layer and a second low-k dielectric layer. The structure comprises a dielectric plug between portions of the first low-k dielectric layer and the second low-dielectric layer.

Abstract: Embodiments of the invention include a method of forming an integrated circuit having a single-damascene line-via interconnect. The method includes forming a via trench in a first dielectric layer. A first portion of a barrier layer is formed within the via trench, and a second portion of the barrier layer is formed over the first dielectric layer. A conductive region is formed and includes a conductive via element and a conductive via overburden. The conductive via element is within the via trench; a first portion of the conductive via overburden is over the second portion of the barrier layer; and a second portion of the conductive via overburden is over the conductive via. Planarization is applied to the conductive region and stopped at the second portion of the barrier layer. The conductive via element is coupled at a line-via interface to a conductive line of the single-damascene line-via interconnect.

Abstract: A method including forming a dual damascene interconnect structure comprising a metal wire above a via, recessing the metal wire to form a trench, depositing a liner along a bottom and a sidewall of the trench, and forming a new metal wire in the trench. The method may also include forming a dual damascene interconnect structure comprising a metal wire above a via, recessing the metal wire to form a trench, depositing a liner along a bottom and a sidewall of the trench, removing the liner along the bottom of the trench, and forming a new metal wire in the trench.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A first set of spacers are formed on the sidewalls of a bottom electrode. A reference layer is formed on the spacers and the bottom electrode. A second set of spacers are formed on the sidewalls of the first set of spacers and the reference layer. A tunnel barrier is formed on the reference layer and the second set of spacers. A free layer is formed on the tunnel barrier, where a width of the free layer is greater than a width of the reference layer. A metal hardmask is formed on the free layer. A third set of spacers are formed on the sidewalls of the metal hardmask, the free layer, the tunnel barrier, and the second set of spacers.

Abstract: Provided is a semiconductor device and corresponding method of fabricating the same. The semiconductor device comprises a plurality of bottom lines. One or more top vias are arranged on top of the plurality of bottom lines. One or more electronic fuses (eFuses) are also arranged on top of the plurality of bottom lines. Each eFuse of the one or more eFuses is a via having a smaller critical dimension that the one or more top vias. A plurality of top lines are arranged on top of the one or more top vias and the one or more eFuses.

Abstract: A memory device includes a bottom electrode having an uppermost surface, a first sidewall, and a second sidewall. The memory device further includes a dielectric layer covering the uppermost surface and the first and second sidewalls of the bottom electrode such that an uppermost surface of the dielectric layer is arranged higher than the uppermost surface of the bottom electrode. The memory device further includes a metal body in direct contact with the uppermost surface of the bottom electrode and extending through the dielectric layer to the uppermost surface of the dielectric layer. The memory device further includes a memory component arranged in direct contact with the metal body and with the uppermost surface of the dielectric layer.