Patents by Inventor Koichi Nagasawa

Koichi Nagasawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220390783
    Abstract: It is an object of the present disclosure to dispose an optical element on a lower surface side of transistors without being influenced by heat treatment in a transistor forming process such that peeling, displacement, and the like do not easily occur. A transistor array substrate includes: a first substrate (110) including transistors (113) arranged in an array; and a second substrate (120) including an optical element (122), in which the transistors are arranged on a front surface side of the first substrate, and the second substrate is bonded to a back surface of the first substrate by plasma bonding treatment.
    Type: Application
    Filed: October 19, 2020
    Publication date: December 8, 2022
    Inventors: KOICHI AMARI, KOICHI NAGASAWA, HITOSHI TSUNO, YOSHIHIKO KAJIYA, SHINTARO NAKANO, TSUYOSHI OKAZAKI, AKIKO TORIYAMA, YOSHITAKA YAGI, KEIICHI MAEDA, TAKASHI SAKAIRI, TSUTOMU TANAKA
  • Patent number: 11374082
    Abstract: An electronic device of the technology includes: a plurality of first wiring patterns that are electrically coupled to each other partially, and each extend in a first direction; an organic insulating layer that is provided on the first wiring patterns; and a second wiring pattern that is provided on the organic insulating layer.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: June 28, 2022
    Assignee: Sony Group Corporation
    Inventors: Koichi Nagasawa, Hirofumi Fujioka, Tomoaki Honda
  • Patent number: 10928679
    Abstract: An optical compensation element includes a first member that includes a first transparent substrate, a first alignment film, and a first phase difference layer and a second member that includes a second transparent substrate, a second alignment film, and a second phase difference layer. In the optical compensation element, a first inorganic barrier layer is formed on a surface of the first phase difference layer, where the surface faces the second member a second inorganic barrier layer is formed on a surface of the second phase difference layer, where the surface faces the second member and the first inorganic barrier layer and the second inorganic barrier layer are bonded by an adhesive layer.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: February 23, 2021
    Assignee: SONY CORPORATION
    Inventors: Akiko Toriyama, Koichi Nagasawa, Tsuyoshi Okazaki
  • Patent number: 10903251
    Abstract: A display device according to the present disclosure includes: a transistor section (100) that includes a gate insulating film (130), a semiconductor layer (140), and a gate electrode layer (120), the semiconductor layer being laminated on the gate insulating film, the gate electrode film being laminated on an opposite side to the semiconductor layer of the gate insulating film; a first capacitor section (200) that includes a first metal film (210) and a second metal film (220), the first metal film being disposed at a same level as wiring layers (161, 162) that are electrically connected to the semiconductor layer and is disposed over the transistor section, the second metal film being disposed over the first metal film with a first interlayer insulating film (152) in between; and a display element that is configured to be controlled by the transistor section.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: January 26, 2021
    Assignee: Sony Corporation
    Inventors: Hitoshi Tsuno, Koichi Nagasawa
  • Publication number: 20210002309
    Abstract: A silane coupling material according to an embodiment of the present disclosure is represented by the following general formula (1) and includes hydrocarbon groups having numbers of carbon atoms different from each other in A and B.
    Type: Application
    Filed: February 15, 2019
    Publication date: January 7, 2021
    Inventors: YOSHITAKA YAGI, KOICHI NAGASAWA
  • Publication number: 20200127020
    Abstract: A display device according to the present disclosure includes: a transistor section (100) that includes a gate insulating film (130), a semiconductor layer (140), and a gate electrode layer (120), the semiconductor layer being laminated on the gate insulating film, the gate electrode film being laminated on an opposite side to the semiconductor layer of the gate insulating film; a first capacitor section (200) that includes a first metal film (210) and a second metal film (220), the first metal film being disposed at a same level as wiring layers (161, 162) that are electrically connected to the semiconductor layer and is disposed over the transistor section, the second metal film being disposed over the first metal film with a first interlayer insulating film (152) in between; and a display element that is configured to be controlled by the transistor section.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 23, 2020
    Inventors: Hitoshi TSUNO, Koichi NAGASAWA
  • Patent number: 10566356
    Abstract: A display device according to the present disclosure includes: a transistor section (100) that includes a gate insulating film (130), a semiconductor layer (140), and a gate electrode layer (120), the semiconductor layer being laminated on the gate insulating film, the gate electrode film being laminated on an opposite side to the semiconductor layer of the gate insulating film; a first capacitor section (200) that includes a first metal film (210) and a second metal film (220), the first metal film being disposed at a same level as wiring layers (161, 162) that are electrically connected to the semiconductor layer and is disposed over the transistor section, the second metal film being disposed over the first metal film with a first interlayer insulating film (152) in between; and a display element that is configured to be controlled by the transistor section.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: February 18, 2020
    Assignee: Sony Corporation
    Inventors: Hitoshi Tsuno, Koichi Nagasawa
  • Patent number: 10527893
    Abstract: A pixel array substrate structure includes: first and second planarizing films sequentially stacked on a substrate where a circuit unit is formed; and a relay wire formed between the first and second planarizing films, in which the relay wire electrically connects a first contact portion formed on the first planarizing film and connected to the circuit unit with a second contact portion formed at a position different from the first contact portion when seen from above, on the second planarizing film.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: January 7, 2020
    Assignee: Japan Display Inc.
    Inventors: Koichi Nagasawa, Masaya Tamaki, Shuji Hayashi, Masaaki Kabe, Yoko Fukunaga
  • Publication number: 20200006459
    Abstract: An electronic device of the technology includes: a plurality of first wiring patterns that are electrically coupled to each other partially, and each extend in a first direction; an organic insulating layer that is provided on the first wiring patterns; and a second wiring pattern that is provided on the organic insulating layer.
    Type: Application
    Filed: September 10, 2019
    Publication date: January 2, 2020
    Inventors: Koichi Nagasawa, Hirofumi Fujioka, Tomoaki Honda
  • Publication number: 20190204647
    Abstract: An optical compensation element 10 includes: a first member 20 that includes a first transparent substrate 121, a first alignment film 122, and a first phase difference layer 123; and a second member 30 that includes a second transparent substrate 221, a second alignment film 222, and a second phase difference layer 223. In the optical compensation element 10, a first inorganic barrier layer 124 is formed on a surface of the first phase difference layer 123, where the surface faces the second member 30; a second inorganic barrier layer 124 is formed on a surface of the second phase difference layer 223, where the surface faces the second member 20; and the first inorganic barrier layer 124 and the second inorganic barrier layer 224 are bonded by an adhesive layer 40.
    Type: Application
    Filed: July 26, 2017
    Publication date: July 4, 2019
    Inventors: AKIKO TORIYAMA, KOICHI NAGASAWA, TSUYOSHI OKAZAKI
  • Patent number: 10341475
    Abstract: A display unit includes: a display layer including a pixel electrode; a semiconductor layer provided in a layer below the display layer, the semiconductor layer including a wiring layer that includes a material removable by an etchant by which the pixel electrode is also removable; and a terminal section configured to electrically connect the semiconductor layer to an external circuit, the terminal section including a first electrically-conductive layer made of a material same as a material of the wiring layer.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: July 2, 2019
    Assignee: Sony Corporation
    Inventors: Koichi Nagasawa, Hirofumi Fujioka, Tomoki Sato, Tomotaka Nishikawa
  • Patent number: 10217777
    Abstract: A display device according to the present disclosure includes: a transistor section (100) that includes a gate insulating film (130), a semiconductor layer (140), and a gate electrode layer (120), the semiconductor layer being laminated on the gate insulating film, the gate electrode film being laminated on an opposite side to the semiconductor layer of the gate insulating film; a first capacitor section (200) that includes a first metal film (210) and a second metal film (220), the first metal film being disposed at a same level as wiring layers (161, 162) that are electrically connected to the semiconductor layer and is disposed over the transistor section, the second metal film being disposed over the first metal film with a first interlayer insulating film (152) in between; and a display element that is configured to be controlled by the transistor section.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: February 26, 2019
    Assignee: Sony Corporation
    Inventors: Hitoshi Tsuno, Koichi Nagasawa
  • Publication number: 20180301477
    Abstract: A display device according to the present disclosure includes: a transistor section (100) that includes a gate insulating film (130), a semiconductor layer (140), and a gate electrode layer (120), the semiconductor layer being laminated on the gate insulating film, the gate electrode film being laminated on an opposite side to the semiconductor layer of the gate insulating film; a first capacitor section (200) that includes a first metal film (210) and a second metal film (220), the first metal film being disposed at a same level as wiring layers (161, 162) that are electrically connected to the semiconductor layer and is disposed over the transistor section, the second metal film being disposed over the first metal film with a first interlayer insulating film (152) in between; and a display element that is configured to be controlled by the transistor section.
    Type: Application
    Filed: June 21, 2018
    Publication date: October 18, 2018
    Inventors: Hitoshi TSUNO, Koichi NAGASAWA
  • Patent number: 10048548
    Abstract: A pixel array substrate structure includes: first and second planarizing films sequentially stacked on a substrate where a circuit unit is formed; and a relay wire formed between the first and second planarizing films, in which the relay wire electrically connects a first contact portion formed on the first planarizing film and connected to the circuit unit with a second contact portion formed at a position different from the first contact portion when seen from above, on the second planarizing film.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: August 14, 2018
    Assignee: Japan Display Inc.
    Inventors: Koichi Nagasawa, Masaya Tamaki, Shuji Hayashi, Masaaki Kabe, Yoko Fukunaga
  • Publication number: 20180203307
    Abstract: A pixel array substrate structure includes: first and second planarizing films sequentially stacked on a substrate where a circuit unit is formed; and a relay wire formed between the first and second planarizing films, in which the relay wire electrically connects a first contact portion formed on the first planarizing film and connected to the circuit unit with a second contact portion formed at a position different from the first contact portion when seen from above, on the second planarizing film.
    Type: Application
    Filed: March 13, 2018
    Publication date: July 19, 2018
    Inventors: Koichi Nagasawa, Masaya Tamaki, Shuji Hayashi, Masaaki Kabe, Yoko Fukunaga
  • Publication number: 20180191880
    Abstract: A display unit includes: a display layer including a pixel electrode; a semiconductor layer provided in a layer below the display layer, the semiconductor layer including a wiring layer that includes a material removable by an etchant by which the pixel electrode is also removable; and a terminal section configured to electrically connect the semiconductor layer to an external circuit, the terminal section including a first electrically-conductive layer made of a material same as a material of the wiring layer.
    Type: Application
    Filed: March 1, 2018
    Publication date: July 5, 2018
    Inventors: Koichi NAGASAWA, Hirofumi FUJIOKA, Tomoki SATO, Tomotaka NISHIKAWA
  • Patent number: 9935135
    Abstract: A display device according to the present disclosure includes: a transistor section (100) that includes a gate insulating film (130), a semiconductor layer (140), and a gate electrode layer (120), the semiconductor layer being laminated on the gate insulating film, the gate electrode film being laminated on an opposite side to the semiconductor layer of the gate insulating film; a first capacitor section (200) that includes a first metal film (210) and a second metal film (220), the first metal film being disposed at a same level as wiring layers (161, 162) that are electrically connected to the semiconductor layer and is disposed over the transistor section, the second metal film being disposed over the first metal film with a first interlayer insulating film (152) in between; and a display element that is configured to be controlled by the transistor section.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: April 3, 2018
    Assignee: SONY CORPORATION
    Inventors: Hitoshi Tsuno, Koichi Nagasawa
  • Publication number: 20180047761
    Abstract: A display device according to the present disclosure includes: a transistor section (100) that includes a gate insulating film (130), a semiconductor layer (140), and a gate electrode layer (120), the semiconductor layer being laminated on the gate insulating film, the gate electrode film being laminated on an opposite side to the semiconductor layer of the gate insulating film; a first capacitor section (200) that includes a first metal film (210) and a second metal film (220), the first metal film being disposed at a same level as wiring layers (161, 162) that are electrically connected to the semiconductor layer and is disposed over the transistor section, the second metal film being disposed over the first metal film with a first interlayer insulating film (152) in between; and a display element that is configured to be controlled by the transistor section.
    Type: Application
    Filed: October 26, 2017
    Publication date: February 15, 2018
    Inventors: Hitoshi TSUNO, Koichi NAGASAWA
  • Publication number: 20170289325
    Abstract: A display unit includes: a display layer including a pixel electrode; a semiconductor layer provided in a layer below the display layer, the semiconductor layer including a wiring layer that includes a material removable by an etchant by which the pixel electrode is also removable; and a terminal section configured to electrically connect the semiconductor layer to an external circuit, the terminal section including a first electrically-conductive layer made of a material same as a material of the wiring layer.
    Type: Application
    Filed: June 21, 2017
    Publication date: October 5, 2017
    Inventors: Koichi NAGASAWA, Hirofumi FUJIOKA, Tomoki SATO, Tomotaka NISHIKAWA
  • Patent number: 9722010
    Abstract: A display device according to the present disclosure includes: a transistor section (100) that includes a gate insulating film (130), a semiconductor layer (140), and a gate electrode layer (120), the semiconductor layer being laminated on the gate insulating film, the gate electrode film being laminated on an opposite side to the semiconductor layer of the gate insulating film; a first capacitor section (200) that includes a first metal film (210) and a second metal film (220), the first metal film being disposed at a same level as wiring layers (161, 162) that are electrically connected to the semiconductor layer and is disposed over the transistor section, the second metal film being disposed over the first metal film with a first interlayer insulating film (152) in between; and a display element that is configured to be controlled by the transistor section.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: August 1, 2017
    Assignee: Sony Corporation
    Inventors: Hitoshi Tsuno, Koichi Nagasawa