Patents by Inventor Koichi Nagasawa
Koichi Nagasawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120162594Abstract: A pixel structure includes: a first planarizing film and a second planarizing film laminated in order on a substrate on which a circuit section is formed; and metallic wiring for electrically connecting two electrodes disposed on the second planarizing film to each other so as to be separated from each other, the metallic wiring being formed between the first planarizing film and the second planarizing film.Type: ApplicationFiled: November 28, 2011Publication date: June 28, 2012Applicant: Sony CorporationInventors: Masaya Tamaki, Koichi Nagasawa, Shuji Hayashi, Masaaki Kabe, Yoko Fukunaga
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Publication number: 20120154736Abstract: A pixel array substrate structure includes: first and second planarizing films sequentially stacked on a substrate where a circuit unit is formed; and a relay wire formed between the first and second planarizing films, in which the relay wire electrically connects a first contact portion formed on the first planarizing film and connected to the circuit unit with a second contact portion formed at a position different from the first contact portion when seen from above, on the second planarizing film.Type: ApplicationFiled: November 28, 2011Publication date: June 21, 2012Applicant: Sony CorporationInventors: Koichi Nagasawa, Masaya Tamaki, Shuji Hayashi, Masaaki Kabe, Yoko Fukunaga
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Publication number: 20110285955Abstract: Disclosed herein is a display device including a first transparent substrate configured to have a surface including a display area and a peripheral area that surrounds the display area and includes an interconnect pattern forming area and an interconnect pattern non-forming area, an interconnect pattern configured to be formed above the interconnect pattern forming area and have light blocking capability, a structural body configured to be formed above the peripheral area in such a manner as to expose the interconnect pattern non-forming area and cover the interconnect pattern, a seal material configured to be formed above the peripheral area in such a manner as to cover the interconnect pattern non-forming area and surround the structural body, a display layer configured to be formed above the display area, and a second transparent substrate configured to be formed over the structural body, the seal material, and the display layer.Type: ApplicationFiled: April 19, 2011Publication date: November 24, 2011Applicant: SONY CORPORATIONInventor: Koichi Nagasawa
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Publication number: 20110287595Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: August 3, 2011Publication date: November 24, 2011Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Publication number: 20110281491Abstract: A method of manufacturing a display device includes the steps of: forming a positive type photoresist above a surface of a first transparent substrate having a transistor formed on the surface thereof so as to cover the transistor; radiating a light from a back surface side of the first transparent substrate to the first transparent substrate having the positive type photoresist formed thereabove, for exposing the positive type photoresist; developing the positive type photoresist thus exposed to selectively leave the positive type photoresist located above the transistor, for forming a spacer; and laminating a second transparent substrate above the surface of the first transparent substrate through the spacer.Type: ApplicationFiled: April 14, 2011Publication date: November 17, 2011Applicant: SONY CORPORATIONInventor: Koichi Nagasawa
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Patent number: 8022550Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: December 30, 2009Date of Patent: September 20, 2011Assignee: Renesas Electronics CorporationInventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Publication number: 20100314621Abstract: An electronic apparatus having a substrate with a bottom gate p-channel type thin film transistor; a resist pattern over the substrate; and a light shielding film operative to block light having a wavelength shorter than 260 nm over at least a channel part of said thin film transistor.Type: ApplicationFiled: August 3, 2010Publication date: December 16, 2010Applicant: SONY CORPORATIONInventors: Koichi Nagasawa, Takashi Yamaguchi, Nobutaka Ozaki, Yasuhiro Kanaya, Hirohisa Takeda, Yasuo Mikami, Yoshifumi Mutoh
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Patent number: 7838402Abstract: A method of manufacturing an electronic apparatus having a resist pattern provided over a substrate provided with a thin film transistor, the method includes the steps of forming by application a resist film over the substrate in the state of covering the thin film transistor, forming a resist pattern by subjecting the resist film to exposure to light and a developing treatment, and irradiating the resist pattern with at least one of ultraviolet light and visible light in a dry atmosphere in the condition where a channel part of the thin film transistor is prevented from being irradiated with light having a wavelength of shorter than 260 nm, wherein a step of heat curing the resist pattern is conducted after the irradiation with at least one of ultraviolet light and visible light.Type: GrantFiled: November 21, 2008Date of Patent: November 23, 2010Assignee: Sony CorporationInventors: Koichi Nagasawa, Takashi Yamaguchi, Nobutaka Ozaki, Yasuhiro Kanaya, Hirohisa Takeda, Yasuo Mikami, Yoshifumi Mutoh
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Publication number: 20100096732Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: December 30, 2009Publication date: April 22, 2010Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Patent number: 7678684Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: July 26, 2007Date of Patent: March 16, 2010Assignee: Renesas Technology Corp.Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Publication number: 20100033668Abstract: A liquid-crystal display device includes a first substrate; a second substrate formed so as to oppose the first substrate; a liquid-crystal layer with a predetermined thickness, the liquid-crystal layer being formed between the first substrate and the second substrate; a planarization film for planarizing the surface of the liquid-crystal layer, the planarization film being formed on the surface of at least one of the first substrate and the second substrate, the surface facing the liquid-crystal layer; and projecting parts that are integrally formed with the planarization film.Type: ApplicationFiled: July 28, 2009Publication date: February 11, 2010Applicant: SONY CORPORATIONInventors: Takeo Koito, Koichi Nagasawa, Shuji Hayashi, Hidehiro Kosaka
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Patent number: 7626267Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: August 13, 2007Date of Patent: December 1, 2009Assignee: Renesas Technology CorporationInventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Patent number: 7554202Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: July 27, 2007Date of Patent: June 30, 2009Assignee: Renesas Technology CorpInventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Publication number: 20090134461Abstract: A method of manufacturing an electronic apparatus having a resist pattern provided over a substrate provided with a thin film transistor, the method includes the steps of forming by application a resist film over the substrate in the state of covering the thin film transistor, forming a resist pattern by subjecting the resist film to exposure to light and a developing treatment, and irradiating the resist pattern with at least one of ultraviolet light and visible light in a dry atmosphere in the condition where a channel part of the thin film transistor is prevented from being irradiated with light having a wavelength of shorter than 260 nm, wherein a step of heat curing the resist pattern is conducted after the irradiation with at least one of ultraviolet light and visible light.Type: ApplicationFiled: November 21, 2008Publication date: May 28, 2009Applicant: SONY CORPORATIONInventors: Koichi Nagasawa, Takashi Yamaguchi, Nobutaka Ozaki, Yasuhiro Kanaya, Hirohisa Takeda, Yasuo Mikami, Yoshifumi Mutoh
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Patent number: 7474003Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: May 23, 2007Date of Patent: January 6, 2009Assignee: Renesas Technology Corp.Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Publication number: 20080173973Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: August 13, 2007Publication date: July 24, 2008Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Publication number: 20080036091Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: July 26, 2007Publication date: February 14, 2008Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Publication number: 20080017990Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: July 27, 2007Publication date: January 24, 2008Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Publication number: 20070222001Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: May 23, 2007Publication date: September 27, 2007Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Patent number: 7274074Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: July 14, 2003Date of Patent: September 25, 2007Assignee: Renesas Technology Corp.Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda