Patents by Inventor Koichi Nagasawa
Koichi Nagasawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7250682Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: October 4, 2004Date of Patent: July 31, 2007Assignee: Renesas Technology Corp.Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Patent number: 7199432Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: August 26, 2004Date of Patent: April 3, 2007Assignee: Renesas Technology Corp.Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Patent number: 7187039Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: April 8, 2005Date of Patent: March 6, 2007Assignee: Renesas Technology Corp.Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Patent number: 7163870Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: September 29, 2004Date of Patent: January 16, 2007Assignee: Renesas Technology Corp.Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Publication number: 20050179110Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: April 8, 2005Publication date: August 18, 2005Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Publication number: 20050040538Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: October 4, 2004Publication date: February 24, 2005Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Publication number: 20050040537Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: September 29, 2004Publication date: February 24, 2005Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Publication number: 20050026405Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: August 26, 2004Publication date: February 3, 2005Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Publication number: 20040012093Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: July 14, 2003Publication date: January 22, 2004Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Patent number: 6664642Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: February 15, 2002Date of Patent: December 16, 2003Assignee: Hitachi, Ltd.Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Patent number: 6433438Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: May 2, 2001Date of Patent: August 13, 2002Assignee: Hitachi, Ltd.Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Patent number: 6423139Abstract: A liquid chemical treatment apparatus includes a coating apparatus for applying a coating liquid such as resist onto the surface of a substantially planar substrate such as a glass substrate. The coating apparatus includes a nozzle with an elongate injection outlet such as a slit with a width substantially the same as that of the substrate, and a liquid circulating passage connected to the nozzle for supplying the coating liquid to the nozzle. Mechanisms are provided with the circulating passage and the nozzle to remove air from the liquid, and to maintain the circulating liquid at a substantially constant temperature and a substantially constant flow rate.Type: GrantFiled: September 15, 1998Date of Patent: July 23, 2002Assignee: Tokyo Ohka Kogyo Co., Ltd.Inventors: Futoshi Shimai, Koichi Nagasawa, Junji Kutsuzawa
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Publication number: 20020074611Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: February 15, 2002Publication date: June 20, 2002Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Publication number: 20010022399Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: May 2, 2001Publication date: September 20, 2001Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Patent number: 6261883Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: March 31, 1998Date of Patent: July 17, 2001Assignee: Hitachi, Ltd.Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Patent number: 6015467Abstract: In a method of removing a coating from an edge of a substrate a solvent reservoir is filled with a solvent to dissolve and remove a photoresist film, the solvent includes one of dipropylene glycol monoalkyl ether, a mixture of this ether and an easily volatile organic solvent (boiling point of 75-130.degree. C., vapor pressure of 5-75 mmHg at 20.degree. C.), and an alkaline aqueous solution, an edge of a substrate W is horizontally inserted in the reservoir, and thereafter, the edge of the substrate W is immersed in the solvent for a period of time, so as to dissolve and remove a coating such as photoresist from the edge of the substrate. The solvent may be filled into the solvent reservoir either before or after the edge of the substrate is inserted therein, and the method may further involve aspirating the solvent from the reservoir after the substrate edge has been inserted therein.Type: GrantFiled: May 21, 1997Date of Patent: January 18, 2000Assignee: Tokyo Ohka Kogyo Co., Ltd.Inventors: Koichi Nagasawa, Naomi Kawaguchi, Futoshi Shimai, Mitsuru Sato, Kouji Harada, Jun Koshiyama
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Patent number: 5849467Abstract: The invention proposes an improved method for the pre-treatment of a photoresist layer formed on a substrate surface prior to pattern-wise exposure of the photoresist layer to actinic rays, in which extraneous portions of the resist layer formed by overspreading of the photoresist solution as in the marginal zone of the patterning area and on the peripheral and back surfaces of the substrate, by dissolving away with a cleaning solution. In contrast to the conventional cleaning solutions consisting entirely or mainly of an organic solvent capable of dissolving the photoresist composition, the cleaning solution used in the inventive method is an aqueous alkaline solution containing a water-soluble alkaline compound dissolved in an aqueous medium consisting of water and a limited amount of a water-miscible organic solvent such as monohydric alcohols, alkyleneglycol monoalkyl ethers and aprotic solvents. The cleaning solution may optionally contain an anti-corrosion agent.Type: GrantFiled: January 28, 1997Date of Patent: December 15, 1998Assignee: Tokyo Ohka Kogyo Co., Ltd.Inventors: Mitsuru Sato, Naomi Nagatsuka, Koichi Nagasawa, Hutoshi Shimai, Kouji Harada
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Patent number: 5785759Abstract: A rotating cup type liquid supply device comprises an inner cup 3, a vacuum chuck 5 disposed in the center of a bottom surface of the inner cup 3 for holding thereon a planar material W to be treated, and a tray 7 fixed onto the bottom surface of the inner cup 3 for substantially surrounding the planar material W held by the vacuum chuck 5. The tray is of a substantially rectangular shape in plan view and includes an tapered wall portion 9 turned inwardly along a circumferential wall portion thereof for defining an upper opening 8 of the tray 7. The tray 7 further includes a plurality of drain guiding conduits 10 each extending at a predetermined angle outwardly from an outer peripheral portion thereof. Also, the tray can be provided thereon with the cover having an opening slightly larger than the planar material W.Type: GrantFiled: October 28, 1996Date of Patent: July 28, 1998Assignee: Tokyo Ohka Kogyo Co., Ltd.Inventors: Hiroyoshi Sago, Shigemi Fujiyama, Futoshi Shimai, Koichi Nagasawa
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Patent number: 5159260Abstract: This reference voltage generator device detects a voltage corresponding to an energy gap of a semiconductor, or a voltage of a value close thereto, or a voltage based on an energy level of a semiconductor, and generates the detected voltage as a reference voltage. The reference voltage is generated by detecting a difference of threshold voltages of first and second insulated gate field-effect transistors (IGFETs). Gate electrodes of the first and second IGFETs are formed on gate insulating films which are formed on different surface areas of an identical semiconductor substrate under substantially the same conditions. The gate electrodes of the first and second IGFETs are respectively made of two semiconductors which are selected from among a semiconductor of a first conductivity type, a semiconductor of a second conductivity type and an intrinsic semiconductor made of an identical semiconductor material, and which have Fermi energy levels of values different from each other.Type: GrantFiled: January 7, 1987Date of Patent: October 27, 1992Assignee: Hitachi, Ltd.Inventors: Kanji Yoh, Osamu Yamashiro, Satoshi Meguro, Koichi Nagasawa, Kotaro Nishimura, Harumi Wakimoto, Kazutaka Narita
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Patent number: 5061985Abstract: With the reduction in the size of semiconductor integrated circuit devices, there have been increases in the resistance at the contact portions of metal interconnections and in the incidence of contact failure. To solve these problems, the present invention provides a novel interconnection structure.Type: GrantFiled: June 12, 1989Date of Patent: October 29, 1991Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.Inventors: Hideo Meguro, Yoshiaki Yoshiura, Tatsuo Itagaki, Ken Uchida, Tsuneo Satoh, Seiichi Ichihara, Koichi Nagasawa