Patents by Inventor Koichiro Ishibashi

Koichiro Ishibashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150220095
    Abstract: A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.
    Type: Application
    Filed: April 13, 2015
    Publication date: August 6, 2015
    Inventors: Masafumi ONOUCHI, Kazuo OTSUGA, Yasuto IGARASHI, Sadayuki MORITA, Koichiro ISHIBASHI, Kazumasa YANAGISAWA
  • Publication number: 20150155031
    Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.
    Type: Application
    Filed: July 3, 2014
    Publication date: June 4, 2015
    Inventors: Kenichi OSADA, Koichiro ISHIBASHI, Yoshikazu SAITOH, Akio NISHIDA, Masaru NAKAMICHI, Naoki KITAI
  • Patent number: 9030176
    Abstract: A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: May 12, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Masafumi Onouchi, Kazuo Otsuga, Yasuto Igarashi, Sadayuki Morita, Koichiro Ishibashi, Kazumasa Yanagisawa
  • Patent number: 9010236
    Abstract: A linear actuator includes a cylinder main body, which is provided at one end thereof with a lock mechanism capable of restricting displacement of a slide table. The lock mechanism is equipped with a lock plate and a sub-piston. The lock plate is rotatable toward a side of the slide table by an elastic force of a spring, inserted into an insertion groove, and restricts displacement of the slide table. The sub-piston is displaced by a pressure fluid supplied to a supply port, and releases a displacement restricted state of the slide table by the lock plate.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: April 21, 2015
    Assignee: SMC Kabushiki Kaisha
    Inventors: Koichiro Ishibashi, Motohiro Sato, Toshio Sato
  • Patent number: 8998491
    Abstract: A linear actuator includes a guide mechanism and a retainer. On a guide block of the guide mechanism, a pair of ball-circulating grooves is formed on the lower surface that faces a cylinder body. Multiple balls are loaded in the ball-circulating grooves. Paired cover blocks are respectively mounted on the two ends of the guide block. The retainer has the form of paired ball clips, which are formed as arms to engage with the cover blocks when the clips are inserted in the ball-circulating grooves to hold the balls. Paired cover plates are respectively mounted on the end faces of the cover blocks, and arm-shaped cover clips are mounted so as to hold the cover plates. The cover plates, the cover blocks, and the guide block are thereby integrally linked.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: April 7, 2015
    Assignee: SMC Kabushiki Kaisha
    Inventors: Koichiro Ishibashi, Seiji Takanashi, Motohiro Sato, Toshio Sato
  • Patent number: 8955424
    Abstract: A linear actuator includes a cylinder main body. With respect to the cylinder main body, a slide table is disposed for reciprocal displacement through a guide mechanism, which is disposed on the cylinder main body. A stopper mechanism having a stopper bolt is disposed on one end of the slide table centrally in a widthwise direction perpendicular to the longitudinal direction of the slide table. In addition, when the slide table is displaced along the cylinder main body, an end of the stopper bolt comes into abutment with an end of a cover of the guide mechanism, whereupon the slide table becomes engaged therewith and movement of the slide table is stopped.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: February 17, 2015
    Assignee: SMC Kabushiki Kaisha
    Inventors: Koichiro Ishibashi, Seiji Takanashi, Motohiro Sato, Jiro Mandokoro, Koji Hara, Toshio Sato
  • Patent number: 8939064
    Abstract: The present invention relates to a linear actuator. A slide table of the linear actuator includes a table main body and an end plate connected to another end of the table main body. On a base portion of the table main body, four workpiece retaining holes are formed, and fitting seats are disposed respectively about the workpiece retaining holes on radial outer sides thereof. The fitting seats are formed at the same time that the table main body is formed by press molding.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: January 27, 2015
    Assignee: SMC Kabushiki Kaisha
    Inventors: Koichiro Ishibashi, Seiji Takanashi, Motohiro Sato, Jiro Mandokoro, Koji Hara, Toshio Sato
  • Publication number: 20140219010
    Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
    Type: Application
    Filed: April 4, 2014
    Publication date: August 7, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Masanao Yamaoka, Koichiro Ishibashi, Shigezumi Matsui, Kenichi Osada
  • Patent number: 8797791
    Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: August 5, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitoh, Akio Nishida, Masaru Nakamichi, Naoki Kitai
  • Publication number: 20140133787
    Abstract: A linear actuator. On a guide block that configures a guide mechanism, a pair of ball-circulating grooves is formed on the lower surface that faces a cylinder body and multiple balls are loaded in the ball-circulating grooves. Paired cover blocks are respectively mounted on the two ends of the guide block. Paired ball clips, which are formed as arms, are engaged with the cover blocks when the clips are inserted in the ball-circulating grooves and are holding the balls. Paired cover plates are respectively mounted on the end faces of the cover blocks, and arm-shaped cover clips are mounted so as to hold the cover plates. The cover plates, the cover blocks and the guide block are thereby integrally linked.
    Type: Application
    Filed: June 19, 2012
    Publication date: May 15, 2014
    Applicant: SMC KABUSHIKI KAISHA
    Inventors: Koichiro Ishibashi, Seiji Takanashi, Motohiro Sato, Toshio Sato
  • Publication number: 20140126278
    Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
    Type: Application
    Filed: January 9, 2014
    Publication date: May 8, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji NII, Shigeki OBAYASHI, Hiroshi MAKINO, Koichiro ISHIBASHI, Hirofumi SHINOHARA
  • Patent number: 8711607
    Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: April 29, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Masanao Yamaoka, Koichiro Ishibashi, Shigezumi Matsui, Kenichi Osada
  • Patent number: 8683911
    Abstract: A linear actuator includes a guide block constituting a guide mechanism. In the guide block, a pair of installation grooves are formed in a lower surface facing toward a cylinder main body. Ball circulation members having therein ball circulation holes are installed respectively in the installation grooves. Additionally, ball circulation passages through which balls circulate are provided. The ball circulation passages are made up from roll-reversing sections disposed on opposite ends of the ball circulation members, the ball circulation holes, second ball guide grooves formed in both side surfaces of the guide block, and first ball guide grooves of the slide table.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: April 1, 2014
    Assignee: SMC Kabushiki Kaisha
    Inventors: Koichiro Ishibashi, Seiji Takanashi, Motohiro Sato, Jiro Mandokoro, Koji Hara, Toshio Sato
  • Publication number: 20140069271
    Abstract: A coupling structure for a piston used in a fluid-pressure cylinder. The piston in the fluid-pressure cylinder includes a piston hole that runs through a central part of the piston in an axial direction thereof. One end of a piston rod and a coupling body coupled to the one end are inserted into the piston hole. The coupling body includes: a main part that contacts the one end of the piston rod; and an angled part formed around the main part and inclined at a prescribed angle with respect thereto. When the coupling body is subjected to pressure inside the piston hole, the diameter of the coupling body increases and a pointed edge of the angled part engages with an inner surface of the piston hole such that the coupling body couples the piston and the piston rod.
    Type: Application
    Filed: May 21, 2012
    Publication date: March 13, 2014
    Applicant: SMC KABUSHIKI KAISHA
    Inventors: Koichiro Ishibashi, Koji Hara, Toshio Sato
  • Patent number: 8630142
    Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: January 14, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Koji Nii, Shigeki Obayashi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
  • Publication number: 20130336827
    Abstract: An open end of a cylinder main body is blocked by a cap, which includes a main body portion, and an outer edge portion that bends from the main body portion toward the open end of the cylinder main body, a distal end of the outer edge portion being locked with an inner circumferential wall. When a piston comes into abutment against the main body portion, a space is formed by the outer edge portion, the inner circumferential wall, and the end surface of the piston. A first port is disposed so as to communicate with the space, whereby the space serves as a space into which the pressure fluid is introduced.
    Type: Application
    Filed: May 23, 2013
    Publication date: December 19, 2013
    Applicant: SMC Kabushiki Kaisha
    Inventors: Koichiro ISHIBASHI, Koji HARA, Toshio SATO
  • Publication number: 20130229860
    Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.
    Type: Application
    Filed: April 18, 2013
    Publication date: September 5, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitoh, Akio Nishida, Masaru Nakamichi, Naoki Kitai
  • Patent number: 8482083
    Abstract: Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: July 9, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Osada, Masataka Minami, Shuji Ikeda, Koichiro Ishibashi
  • Patent number: 8437179
    Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: May 7, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitoh, Akio Nishida, Masaru Nakamichi, Naoki Kitai
  • Publication number: 20130049131
    Abstract: Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines.
    Type: Application
    Filed: September 14, 2012
    Publication date: February 28, 2013
    Inventors: Kenichi OSADA, Masataka Minami, Shuji Ikeda, Koichiro Ishibashi